KMAC/MASKED Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.100s	911.059us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.010s	21.414us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	87.447us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.540s	12.159ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.590s	1.297ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.780s	92.793us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	87.447us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.297ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.700s	18.446us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	58.419us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	36.626m	164.801ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.620m	3.705ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.962m	361.894ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.938m	60.420ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.429m	50.065ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.490s	1.021ms	1	1	100.00
		kmac_test_vectors_shake_128	3.364m	89.867ms	1	1	100.00
		kmac_test_vectors_shake_256	1.362m	3.490ms	1	1	100.00
		kmac_test_vectors_kmac	3.590s	77.636us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.180s	108.910us	1	1	100.00
V2	sideload	kmac_sideload	6.130s	1.059ms	1	1	100.00
V2	app	kmac_app	3.403m	9.854ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.054m	22.811ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.905m	6.366ms	1	1	100.00
V2	error	kmac_error	4.398m	15.030ms	1	1	100.00
V2	key_error	kmac_key_error	3.060s	511.585us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.910s	401.507us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.940s	25.450us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.000s	70.653us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	39.410s	3.133ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.230s	79.639us	1	1	100.00
V2	stress_all	kmac_stress_all	11.374m	41.881ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.790s	19.889us	1	1	100.00
V2	alert_test	kmac_alert_test	2.220s	18.396us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.340s	113.181us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.340s	113.181us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.010s	21.414us	1	1	100.00
		kmac_csr_rw	1.810s	87.447us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.297ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	222.690us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.010s	21.414us	1	1	100.00
		kmac_csr_rw	1.810s	87.447us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.297ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	222.690us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.260s	39.503us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.260s	39.503us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.260s	39.503us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.260s	39.503us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.670s	1.423ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	29.000s	2.693ms	1	1	100.00
		kmac_tl_intg_err	2.690s	58.902us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.690s	58.902us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.230s	79.639us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.100s	911.059us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.130s	1.059ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.260s	39.503us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	29.000s	2.693ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	29.000s	2.693ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	29.000s	2.693ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.100s	911.059us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.230s	79.639us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	29.000s	2.693ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.585m	200.000ms	0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.100s	911.059us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.035m	30.482ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.9467268185062319525744552968432561707979768468316324218158545943234457041741
      Line 218, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_mubi/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---