KMAC/UNMASKED Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.230s	3.304ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	54.002us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.600s	34.344us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.790s	505.158us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.970s	200.019us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.240s	165.758us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.600s	34.344us	1	1	100.00
		kmac_csr_aliasing	3.970s	200.019us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.730s	12.864us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.890s	224.084us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.287m	21.583ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.875m	30.802ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.682m	68.982ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.020s	9.551ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.550s	3.390ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.970s	924.118us	1	1	100.00
		kmac_test_vectors_shake_128	30.865m	104.832ms	1	1	100.00
		kmac_test_vectors_shake_256	3.382m	5.550ms	1	1	100.00
		kmac_test_vectors_kmac	2.690s	196.080us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.990s	1.526ms	1	1	100.00
V2	sideload	kmac_sideload	3.198m	7.718ms	1	1	100.00
V2	app	kmac_app	1.179m	20.830ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.982m	16.215ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.962m	67.047ms	1	1	100.00
V2	error	kmac_error	3.338m	61.250ms	1	1	100.00
V2	key_error	kmac_key_error	2.430s	687.090us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.380s	133.666us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.280s	1.096ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.100s	843.908us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	35.180s	8.998ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	7.180s	1.219ms	1	1	100.00
V2	stress_all	kmac_stress_all	7.314m	10.973ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.680s	20.269us	1	1	100.00
V2	alert_test	kmac_alert_test	1.860s	23.008us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.570s	253.697us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.570s	253.697us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	54.002us	1	1	100.00
		kmac_csr_rw	1.600s	34.344us	1	1	100.00
		kmac_csr_aliasing	3.970s	200.019us	1	1	100.00
		kmac_same_csr_outstanding	2.490s	162.781us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	54.002us	1	1	100.00
		kmac_csr_rw	1.600s	34.344us	1	1	100.00
		kmac_csr_aliasing	3.970s	200.019us	1	1	100.00
		kmac_same_csr_outstanding	2.490s	162.781us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.160s	91.239us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.160s	91.239us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.160s	91.239us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.160s	91.239us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	413.159us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.210s	11.681ms	1	1	100.00
		kmac_tl_intg_err	3.070s	123.880us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.070s	123.880us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	7.180s	1.219ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.230s	3.304ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.198m	7.718ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.160s	91.239us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.210s	11.681ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.210s	11.681ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.210s	11.681ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.230s	3.304ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	7.180s	1.219ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.210s	11.681ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.033m	7.903ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.230s	3.304ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.580s	1.379ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.108010833389052896399821141584660248115943753366853905107960631815718237164394
      Line 125, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1378975928 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1378975928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---