PATTGEN Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: `91d1222`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	52.457us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	14.876us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	48.753us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	215.105us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	35.677us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	26.008us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	48.753us	1	1	100.00
		pattgen_csr_aliasing	4.000s	35.677us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	37.000s	5.601ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	25.000s	10.370ms	1	1	100.00
V2	error	pattgen_error	4.000s	117.572us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.000s	178.751us	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	119.284us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	44.315us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	186.179us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	186.179us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	14.876us	1	1	100.00
		pattgen_csr_rw	4.000s	48.753us	1	1	100.00
		pattgen_csr_aliasing	4.000s	35.677us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	95.525us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	14.876us	1	1	100.00
		pattgen_csr_rw	4.000s	48.753us	1	1	100.00
		pattgen_csr_aliasing	4.000s	35.677us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	95.525us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	133.558us	1	1	100.00
		pattgen_sec_cm	4.000s	86.126us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	133.558us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.000s	14.965ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.167m	10.016ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.17317737466404456788814238432689434887812893934585393206374667417768062750698
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016251382 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4f387790, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10016251382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:925) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.2831775699869424220073089743000195007911225639595007166768510770861129464721
Line 279, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4538237252 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4538247370 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4538247370 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 4538372371 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.84674975676722599542407681941981202825951213658498328411980345391904445510054
    Line 142, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 178750933 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10368
```