ROM_CTRL/32KB Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.860s 137.162us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.530s 214.001us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.140s 6.164ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.390s 128.982us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.540s 1.161ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.750s 136.859us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.140s 6.164ms 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 1.161ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.760s 171.218us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.740s 167.895us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.700s 140.407us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.490s 2.116ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.250s 219.600us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.050s 126.130us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.170s 173.986us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.170s 173.986us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.530s 214.001us 1 1 100.00
rom_ctrl_csr_rw 5.140s 6.164ms 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 1.161ms 1 1 100.00
rom_ctrl_same_csr_outstanding 4.100s 209.871us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.530s 214.001us 1 1 100.00
rom_ctrl_csr_rw 5.140s 6.164ms 1 1 100.00
rom_ctrl_csr_aliasing 4.540s 1.161ms 1 1 100.00
rom_ctrl_same_csr_outstanding 4.100s 209.871us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.380s 1.466ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
rom_ctrl_tl_intg_err 23.060s 1.740ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.860s 137.162us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.860s 137.162us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.860s 137.162us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.060s 1.740ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.250s 219.600us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.653m 14.033ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.380s 1.466ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.096m 982.028us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.885m 3.478ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00