ROM_CTRL/64KB Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 11.080s 768.025us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.440s 300.701us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 10.440s 1.035ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.940s 293.259us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.210s 726.818us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.130s 219.980us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 10.440s 1.035ms 1 1 100.00
rom_ctrl_csr_aliasing 6.210s 726.818us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 9.010s 289.682us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 13.010s 1.059ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.940s 1.068ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.450s 2.778ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.190s 1.083ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 10.400s 1.063ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.770s 632.027us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.770s 632.027us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.440s 300.701us 1 1 100.00
rom_ctrl_csr_rw 10.440s 1.035ms 1 1 100.00
rom_ctrl_csr_aliasing 6.210s 726.818us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.540s 291.235us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.440s 300.701us 1 1 100.00
rom_ctrl_csr_rw 10.440s 1.035ms 1 1 100.00
rom_ctrl_csr_aliasing 6.210s 726.818us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.540s 291.235us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.960s 753.092us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
rom_ctrl_tl_intg_err 37.670s 319.636us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 11.080s 768.025us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 11.080s 768.025us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 11.080s 768.025us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.670s 319.636us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.190s 1.083ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.273m 4.818ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.960s 753.092us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.559m 4.212ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 51.030s 8.106ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00