RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.890s 2.509ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.900s 228.031us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.010s 126.091us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.330s 3.315ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.990s 270.061us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 21.910s 10.947ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 7.870s 5.643ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 25.110s 23.568ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 2.235m 65.205ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.940s 763.022us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.040s 145.398us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.020s 616.847us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.230s 162.606us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.000s 109.818us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.680s 1.284ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.940s 155.973us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.100s 267.968us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.940s 763.022us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.110s 336.327us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.490s 513.576us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.020s 616.847us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.630s 31.699us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.910s 479.762us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 3.140s 499.208us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 27.340s 33.281ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.360s 1.145ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.960s 114.526us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.360s 1.145ms 1 1 100.00
rv_dm_csr_rw 3.140s 499.208us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.590s 37.409us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.760s 89.314us 1 1 100.00
V1 TOTAL 27 27 100.00
V2 idcode rv_dm_smoke 2.890s 2.509ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.030s 161.578us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.810s 116.009us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.710s 538.868us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.830s 2.311ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.320s 823.449us 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.980s 101.052us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 1.970s 1.051ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 16.420s 13.662ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.040s 178.036us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.420s 2.277ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.490s 558.616us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.250s 341.060us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 32.530s 15.515ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.720s 75.326us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.970s 466.781us 1 1 100.00
V2 stress_all rv_dm_stress_all 9.410s 4.312ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.680s 152.350us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.880s 114.499us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.880s 114.499us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.360s 1.145ms 1 1 100.00
rv_dm_csr_hw_reset 2.910s 479.762us 1 1 100.00
rv_dm_csr_rw 3.140s 499.208us 1 1 100.00
rv_dm_same_csr_outstanding 6.990s 575.162us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.360s 1.145ms 1 1 100.00
rv_dm_csr_hw_reset 2.910s 479.762us 1 1 100.00
rv_dm_csr_rw 3.140s 499.208us 1 1 100.00
rv_dm_same_csr_outstanding 6.990s 575.162us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.350s 570.376us 1 1 100.00
rv_dm_tl_intg_err 8.460s 2.876ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 8.460s 2.876ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.420s 2.277ms 1 1 100.00
rv_dm_debug_disabled 1.740s 108.937us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.420s 2.277ms 1 1 100.00
rv_dm_debug_disabled 1.740s 108.937us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.890s 2.509ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.820s 237.120us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.740s 74.768us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.740s 74.768us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.820s 237.120us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.770s 46.329us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.660s 12.401us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets