SPI_DEVICE/1R1W Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.500m	122.312ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.790s	114.254us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	100.952us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.070s	4.642ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.520s	866.756us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.660s	42.597us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	100.952us	1	1	100.00
		spi_device_csr_aliasing	10.520s	866.756us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.450s	65.074us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	47.004us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	15.435us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.750s	1.709us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	1.725us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.560s	188.510us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.560s	188.510us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.530s	1.404ms	1	1	100.00
		spi_device_tpm_sts_read	1.780s	56.457us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	11.720s	962.575us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.450s	1.966ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.970s	552.170us	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.970s	552.170us	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.660s	1.538ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.660s	1.538ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.660s	1.538ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.660s	1.538ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.660s	1.538ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.700s	15.133ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.454m	34.706ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.454m	34.706ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.454m	34.706ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.740s	515.036us	1	1	100.00
		spi_device_read_buffer_direct	10.650s	1.560ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.454m	34.706ms	1	1	100.00
		spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	50.680s	5.717ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.460s	1.565ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.460s	1.565ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.500m	122.312ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	24.050s	9.221ms	1	1	100.00
V2	stress_all	spi_device_stress_all	10.937m	619.824ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.580s	35.885us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	16.809us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.690s	292.886us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.690s	292.886us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.790s	114.254us	1	1	100.00
		spi_device_csr_rw	2.760s	100.952us	1	1	100.00
		spi_device_csr_aliasing	10.520s	866.756us	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	61.382us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.790s	114.254us	1	1	100.00
		spi_device_csr_rw	2.760s	100.952us	1	1	100.00
		spi_device_csr_aliasing	10.520s	866.756us	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	61.382us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.260s	110.401us	1	1	100.00
		spi_device_tl_intg_err	8.940s	462.840us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.940s	462.840us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	37.660s	5.282ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.79117540969658587488651173457464388053264728091666053382161309474888000526639
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1375522 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[23])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1375522 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1375522 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[919])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.107740984969124011011796125041748465691106210506350353247687822508240561513385
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    915335 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    915335 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    991335 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9bc00f [100110111100000000001111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    991335 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x9bc00f [100110111100000000001111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])