SPI_DEVICE/2P Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 2.139m 160.877ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.750s 28.195us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.390s 147.227us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 23.500s 1.929ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 11.900s 6.269ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.740s 289.078us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.390s 147.227us 1 1 100.00
spi_device_csr_aliasing 11.900s 6.269ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.690s 13.542us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.390s 29.707us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.910s 59.544us 1 1 100.00
V2 mem_parity spi_device_mem_parity 2.070s 25.991us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.670s 3.768us 0 1 0.00
V2 tpm_read spi_device_tpm_rw 2.820s 530.281us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 2.820s 530.281us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 9.030s 19.754ms 1 1 100.00
spi_device_tpm_sts_read 1.730s 20.744us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.980s 13.508us 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 10.020s 13.283ms 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 4.460s 370.394us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 4.460s 370.394us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 6.280s 719.395us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 6.280s 719.395us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 6.280s 719.395us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 6.280s 719.395us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 6.280s 719.395us 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 7.550s 8.242ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 6.640s 1.658ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 6.640s 1.658ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 6.640s 1.658ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 3.020s 50.014us 1 1 100.00
spi_device_read_buffer_direct 3.890s 675.232us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 6.640s 1.658ms 1 1 100.00
spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 quad_spi spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 dual_spi spi_device_flash_all 16.100s 1.184ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 3.350s 100.366us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 3.350s 100.366us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 2.139m 160.877ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 1.103m 9.093ms 1 1 100.00
V2 stress_all spi_device_stress_all 7.161m 67.448ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.600s 20.718us 1 1 100.00
V2 intr_test spi_device_intr_test 1.690s 16.294us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.200s 45.999us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.200s 45.999us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.750s 28.195us 1 1 100.00
spi_device_csr_rw 2.390s 147.227us 1 1 100.00
spi_device_csr_aliasing 11.900s 6.269ms 1 1 100.00
spi_device_same_csr_outstanding 3.950s 160.175us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.750s 28.195us 1 1 100.00
spi_device_csr_rw 2.390s 147.227us 1 1 100.00
spi_device_csr_aliasing 11.900s 6.269ms 1 1 100.00
spi_device_same_csr_outstanding 3.950s 160.175us 1 1 100.00
V2 TOTAL 21 22 95.45
V2S tl_intg_err spi_device_sec_cm 2.230s 61.993us 1 1 100.00
spi_device_tl_intg_err 5.570s 391.556us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 5.570s 391.556us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 4.132m 61.953ms 0 1 0.00
TOTAL 31 33 93.94

Failure Buckets