SPI_HOST Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.883m	29.330ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	36.451us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	22.730us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	166.178us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	32.886us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	32.863us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	22.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.886us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	15.226us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	31.889us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	115.893us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	28.000s	5.824ms	1	1	100.00
		spi_host_error_cmd	4.000s	26.065us	1	1	100.00
		spi_host_event	8.000s	343.178us	1	1	100.00
V2	clock_rate	spi_host_speed	17.000s	964.625us	1	1	100.00
V2	speed	spi_host_speed	17.000s	964.625us	1	1	100.00
V2	chip_select_timing	spi_host_speed	17.000s	964.625us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	47.134us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	141.996us	1	1	100.00
V2	cpol_cpha	spi_host_speed	17.000s	964.625us	1	1	100.00
V2	full_cycle	spi_host_speed	17.000s	964.625us	1	1	100.00
V2	duplex	spi_host_smoke	3.883m	29.330ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	3.883m	29.330ms	1	1	100.00
V2	stress_all	spi_host_stress_all	24.000s	589.129us	1	1	100.00
V2	spien	spi_host_spien	8.000s	3.091ms	1	1	100.00
V2	stall	spi_host_status_stall	14.000s	1.060ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	18.000s	6.939ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	28.000s	5.824ms	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	18.295us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	25.414us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	148.150us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	148.150us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	36.451us	1	1	100.00
		spi_host_csr_rw	4.000s	22.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.886us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	29.879us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	36.451us	1	1	100.00
		spi_host_csr_rw	4.000s	22.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.886us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	29.879us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	371.683us	1	1	100.00
		spi_host_sec_cm	4.000s	700.201us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	371.683us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	27.233m	137.710ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.63218980460698757426042954566992668749513611933379527487879823464689937626914
      Line 170, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 137709930538 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaff3d054, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
        UVM_INFO @ 137709930538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---