SRAM_CTRL/MAIN Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.030s	4.297ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	19.095us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.940s	21.530us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	91.989us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.890s	23.969us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.780s	363.757us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.940s	21.530us	1	1	100.00
		sram_ctrl_csr_aliasing	1.890s	23.969us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.726m	5.418ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.677m	10.086ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.615m	24.660ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.718m	5.416ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	9.331m	49.986ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	13.218m	87.761ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.260s	6.855ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.290m	10.892ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	28.790s	2.099ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.508m	56.809ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.620s	2.801ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	27.750s	1.499ms	1	1	100.00
		sram_ctrl_throughput_w_readback	50.930s	5.090ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.029m	22.742ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.120s	991.459us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	39.199m	105.751ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	12.845us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.310s	144.359us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.310s	144.359us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	19.095us	1	1	100.00
		sram_ctrl_csr_rw	1.940s	21.530us	1	1	100.00
		sram_ctrl_csr_aliasing	1.890s	23.969us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	112.861us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	19.095us	1	1	100.00
		sram_ctrl_csr_rw	1.940s	21.530us	1	1	100.00
		sram_ctrl_csr_aliasing	1.890s	23.969us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	112.861us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.650s	29.361ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
		sram_ctrl_tl_intg_err	2.840s	328.326us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.840s	328.326us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.029m	22.742ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.029m	22.742ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.940s	21.530us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.290m	10.892ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.290m	10.892ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.290m	10.892ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.260s	6.855ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	8.190s	2.645ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.650s	29.361ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.370s	2.985ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.030s	4.297ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.030s	4.297ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.290m	10.892ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.260s	6.855ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.030s	4.297ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	3.541us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.980s	1.689ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.117262925168044901963250447443377760119191128981652807045787001109940504022
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2985465698 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1e) != exp (0x56)
        UVM_INFO @ 2985465698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.79614893930909832636193671767562447565981898520087092296104445417005169552098
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2645229608 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2645229608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.58076182875956695408449997744223744705701614756382274692798272686833115697248
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3540847 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3540847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---