SRAM_CTRL/RET Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.650s	381.415us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	47.852us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.410s	20.862us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.880s	134.697us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.720s	26.773us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.950s	43.439us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.410s	20.862us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	26.773us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.720s	1.168ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.140s	247.305us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.950m	6.583ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.868m	11.006ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.500s	8.201ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.941m	8.184ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.700s	1.822ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.148m	3.044ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.800s	264.197us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.575m	23.639ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	52.690s	1.814ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	49.210s	596.644us	1	1	100.00
		sram_ctrl_throughput_w_readback	51.620s	265.125us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.422m	3.738ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.690s	57.493us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.202m	39.869ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.480s	14.392us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.050s	70.768us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.050s	70.768us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	47.852us	1	1	100.00
		sram_ctrl_csr_rw	1.410s	20.862us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	26.773us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	25.536us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	47.852us	1	1	100.00
		sram_ctrl_csr_rw	1.410s	20.862us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	26.773us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	25.536us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.240s	1.687ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
		sram_ctrl_tl_intg_err	2.830s	232.825us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.830s	232.825us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.422m	3.738ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.422m	3.738ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.410s	20.862us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.148m	3.044ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.148m	3.044ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.148m	3.044ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.700s	1.822ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.130s	322.962us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.240s	1.687ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.710s	102.353us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.650s	381.415us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.650s	381.415us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.148m	3.044ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.700s	1.822ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.650s	381.415us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.470s	4.344us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.106m	10.076ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.82252623921648315295889055009636044154646963878532772489731344299142110930406
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 102352766 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x73) != exp (0x7a)
        UVM_INFO @ 102352766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.88080492371905088477458439423700857757497094813020012848797218158355530212094
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4344039 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4344039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---