SYSRST_CTRL Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.440s 2.108ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.830s 2.469ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.750s 2.439ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.640s 2.537ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 12.380s 6.026ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.170s 2.043ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 21.040s 38.808ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.480s 2.672ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 5.650s 2.075ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.170s 2.043ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.480s 2.672ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 4.384m 152.125ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.889m 67.266ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.940s 3.307ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.740s 3.765ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.330s 2.514ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 5.530s 2.144ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.350s 4.405ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.940s 2.622ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.740s 4.871ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.009m 35.001ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 2.319m 68.734ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.290s 2.036ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.150s 2.013ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.810s 2.189ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.810s 2.189ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 12.380s 6.026ms 1 1 100.00
sysrst_ctrl_csr_rw 5.170s 2.043ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.480s 2.672ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.960s 9.812ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 12.380s 6.026ms 1 1 100.00
sysrst_ctrl_csr_rw 5.170s 2.043ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.480s 2.672ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.960s 9.812ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 4.950s 22.447ms 1 1 100.00
sysrst_ctrl_tl_intg_err 26.160s 42.812ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 26.160s 42.812ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 10.220s 16.920ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00