UART Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.240s	305.293us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.470s	15.460us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.600s	15.742us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.700s	177.095us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.670s	58.746us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.670s	37.621us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.600s	15.742us	1	1	100.00
		uart_csr_aliasing	1.670s	58.746us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	57.430s	129.781ms	1	1	100.00
V2	parity	uart_smoke	2.240s	305.293us	1	1	100.00
		uart_tx_rx	57.430s	129.781ms	1	1	100.00
V2	parity_error	uart_intr	28.230s	93.037ms	1	1	100.00
		uart_rx_parity_err	25.880s	16.912ms	1	1	100.00
V2	watermark	uart_tx_rx	57.430s	129.781ms	1	1	100.00
		uart_intr	28.230s	93.037ms	1	1	100.00
V2	fifo_full	uart_fifo_full	33.740s	59.471ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.157m	65.628ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	8.670s	28.699ms	1	1	100.00
V2	rx_frame_err	uart_intr	28.230s	93.037ms	1	1	100.00
V2	rx_break_err	uart_intr	28.230s	93.037ms	1	1	100.00
V2	rx_timeout	uart_intr	28.230s	93.037ms	1	1	100.00
V2	perf	uart_perf	8.100m	13.023ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.040s	1.271ms	1	1	100.00
V2	line_loopback	uart_loopback	4.040s	1.271ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	17.240s	14.875ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.850s	813.228us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.220s	680.265us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.110s	3.708ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.846m	169.110ms	1	1	100.00
V2	stress_all	uart_stress_all	53.750s	847.725ms	1	1	100.00
V2	alert_test	uart_alert_test	1.440s	18.566us	1	1	100.00
V2	intr_test	uart_intr_test	1.440s	12.710us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	828.850us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	828.850us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.470s	15.460us	1	1	100.00
		uart_csr_rw	1.600s	15.742us	1	1	100.00
		uart_csr_aliasing	1.670s	58.746us	1	1	100.00
		uart_same_csr_outstanding	1.650s	40.135us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.470s	15.460us	1	1	100.00
		uart_csr_rw	1.600s	15.742us	1	1	100.00
		uart_csr_aliasing	1.670s	58.746us	1	1	100.00
		uart_same_csr_outstanding	1.650s	40.135us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.700s	144.997us	1	1	100.00
		uart_tl_intg_err	1.700s	184.731us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.700s	184.731us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	21.340s	8.330ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00