CHIP Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: `91d1222`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.976m	2.806ms	1	1	100.00
		chip_sw_example_rom	1.003m	2.360ms	1	1	100.00
		chip_sw_example_manufacturer	2.161m	2.939ms	1	1	100.00
		chip_sw_example_concurrency	2.427m	2.997ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.639m	5.149ms	1	1	100.00
V1	csr_rw	chip_csr_rw	4.756m	5.643ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	38.215m	41.469ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	57.063m	32.605ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	47.630s	2.265ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	57.063m	32.605ms	1	1	100.00
		chip_csr_rw	4.756m	5.643ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	7.270s	246.902us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.904m	4.322ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.904m	4.322ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.904m	4.322ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.790m	4.405ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.790m	4.405ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.037m	4.003ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.041m	4.713ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.614m	4.425ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.478m	13.283ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.781m	3.959ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.700m	8.660ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.309m	4.662ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.309m	4.662ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.879m	3.023ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.358m	2.740ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.050m	4.550ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.061m	2.611ms	1	1	100.00
		chip_tap_straps_testunlock0	7.507m	8.116ms	1	1	100.00
		chip_tap_straps_rma	3.319m	3.776ms	1	1	100.00
		chip_tap_straps_prod	18.005m	19.135ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.904m	2.544ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.178m	8.528ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.770m	5.651ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.770m	5.651ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.213m	7.794ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	34.210m	22.458ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.832m	4.095ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.275m	6.153ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.916m	19.368ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.276m	2.897ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.716m	5.588ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.633m	3.083ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.930m	6.499ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.902m	2.726ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.833m	4.825ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.999m	2.416ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.645m	3.514ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.399m	6.863ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.286m	5.359ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.102m	2.370ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.286m	5.359ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.342m	2.521ms	1	1	100.00
		chip_sw_aes_smoketest	3.003m	2.213ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.148m	3.213ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.507m	2.113ms	1	1	100.00
		chip_sw_csrng_smoketest	2.159m	2.925ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.840m	3.700ms	1	1	100.00
		chip_sw_gpio_smoketest	2.885m	2.710ms	1	1	100.00
		chip_sw_hmac_smoketest	2.467m	3.023ms	1	1	100.00
		chip_sw_kmac_smoketest	3.102m	3.319ms	1	1	100.00
		chip_sw_otbn_smoketest	14.136m	8.602ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.564m	5.962ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.235m	6.705ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.677m	3.078ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.210m	3.377ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.528m	3.539ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.943m	2.546ms	1	1	100.00
		chip_sw_uart_smoketest	3.170m	3.577ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.777m	2.743ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.422m	5.129ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.964h	60.139ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.034m	15.249ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.461m	5.124ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.218m	3.227ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.599m	3.430ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.810h	52.883ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.858h	57.182ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	45.370s	2.508ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	45.370s	2.508ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	57.063m	32.605ms	1	1	100.00
		chip_same_csr_outstanding	17.567m	15.982ms	1	1	100.00
		chip_csr_hw_reset	2.639m	5.149ms	1	1	100.00
		chip_csr_rw	4.756m	5.643ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	57.063m	32.605ms	1	1	100.00
		chip_same_csr_outstanding	17.567m	15.982ms	1	1	100.00
		chip_csr_hw_reset	2.639m	5.149ms	1	1	100.00
		chip_csr_rw	4.756m	5.643ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	13.460s	454.279us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.040s	53.941us	1	1	100.00
		xbar_smoke_large_delays	46.050s	7.652ms	1	1	100.00
		xbar_smoke_slow_rsp	36.530s	4.288ms	1	1	100.00
		xbar_random_zero_delays	7.610s	97.291us	1	1	100.00
		xbar_random_large_delays	5.297m	56.492ms	1	1	100.00
		xbar_random_slow_rsp	1.706m	12.741ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.350s	508.644us	1	1	100.00
		xbar_error_and_unmapped_addr	13.270s	202.556us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	32.670s	1.888ms	1	1	100.00
		xbar_error_and_unmapped_addr	13.270s	202.556us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	54.560s	2.275ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.368m	54.313ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.440s	796.649us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.737m	8.679ms	1	1	100.00
		xbar_stress_all_with_error	2.579m	4.113ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.270m	575.310us	1	1	100.00
		xbar_stress_all_with_reset_error	1.746m	4.101ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.034m	15.249ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.455m	25.892ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.184m	14.960ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.278m	10.770ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.301m	14.810ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.640m	16.093ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.817m	15.516ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.255m	15.032ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.060s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.620s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.680s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.930s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.580s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.250s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.700s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.350s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.500s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.680s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.950s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	28.450s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.960s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.700s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.240s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.680s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	27.560s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	27.680s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.910s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	30.200s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.880s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	28.110s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.230s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	31.720s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	29.620s	10.120us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.343m	10.578ms	1	1	100.00
		rom_e2e_asm_init_dev	38.090m	15.114ms	1	1	100.00
		rom_e2e_asm_init_prod	37.086m	15.648ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.987m	15.662ms	1	1	100.00
		rom_e2e_asm_init_rma	37.625m	14.907ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.562m	15.213ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.778m	14.561ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.565m	15.369ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.951m	16.409ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.021m	18.036ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.021m	18.036ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.515m	2.677ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.276m	2.897ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.879m	2.837ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.623m	3.002ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.838m	7.723ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.087m	3.422ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.100m	5.348ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.409m	5.463ms	1	1	100.00
		chip_plic_all_irqs_10	4.718m	3.388ms	1	1	100.00
		chip_plic_all_irqs_20	5.092m	4.277ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.646m	3.457ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.127m	13.070ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.284m	4.741ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.342m	2.740ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.644m	10.236ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.930m	6.489ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.136m	8.149ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.567m	8.265ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.317h	255.882ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.591m	3.451ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.564m	5.962ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.591m	3.451ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.541m	7.759ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.541m	7.759ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.617m	7.437ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.205m	4.483ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.587m	5.992ms	1	1	100.00
		chip_sw_aes_idle	2.623m	3.002ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.383m	3.027ms	1	1	100.00
		chip_sw_kmac_idle	2.587m	2.771ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.854m	4.651ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.645m	3.593ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.570m	4.508ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.123m	4.359ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.798m	10.791ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.543m	4.556ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.875m	4.824ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.614m	4.477ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.912m	4.580ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.614m	3.609ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.436m	4.134ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.213m	7.794ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.971m	6.191ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.614m	4.477ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.912m	4.580ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.832m	4.095ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.275m	6.153ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.916m	19.368ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.276m	2.897ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.716m	5.588ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.633m	3.083ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.930m	6.499ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.902m	2.726ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.833m	4.825ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.999m	2.416ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.601m	2.854ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.391m	4.516ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.502m	6.663ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.027m	25.301ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.982m	2.977ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.367m	2.797ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.858m	9.855ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.528m	3.568ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.072m	5.962ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.550m	17.385ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	30.306m	18.595ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.213m	7.794ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.072m	4.766ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.548m	3.233ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.930m	6.489ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.429m	6.416ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.257m	2.644ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.653m	5.631ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.942m	2.291ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.294h	35.000ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.258m	2.734ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.194m	6.894ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.258m	2.734ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.429m	6.416ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.175m	2.165ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.774m	15.986ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.744m	5.970ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.275m	6.153ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.949m	4.278ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.832m	4.095ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.806m	44.004ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.774m	15.986ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.556m	3.463ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.806m	44.004ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.289m	4.304ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.634m	4.605ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.487m	5.493ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.487m	5.493ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.700m	3.045ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.633m	3.083ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.383m	3.027ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.382m	3.221ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	13.473m	6.776ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.914m	6.050ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.653m	5.007ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.665m	5.386ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.657m	4.741ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.930m	6.499ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	18.901m	10.157ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.838m	7.723ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.663m	11.323ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.739m	3.169ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.575m	2.914ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.902m	2.726ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.974m	3.117ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	20.280m	8.983ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.587m	2.771ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.100m	5.348ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.061m	2.611ms	1	1	100.00
		chip_tap_straps_rma	3.319m	3.776ms	1	1	100.00
		chip_tap_straps_prod	18.005m	19.135ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.320m	3.343ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	18.670m	9.077ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.478m	3.388ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.806m	44.004ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.500m	3.656ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.658m	7.911ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.072m	6.458ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.112m	5.945ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.848m	9.053ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.214m	8.889ms	1	1	100.00
		chip_prim_tl_access	1.289m	4.304ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.971m	6.191ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.543m	4.556ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.875m	4.824ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.614m	4.477ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.912m	4.580ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.614m	3.609ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.436m	4.134ms	1	1	100.00
		chip_tap_straps_dev	2.061m	2.611ms	1	1	100.00
		chip_tap_straps_rma	3.319m	3.776ms	1	1	100.00
		chip_tap_straps_prod	18.005m	19.135ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.067m	13.927ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.305m	2.902ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.691m	3.224ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.325m	2.865ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.391m	3.074ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.586m	31.000ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.067m	13.927ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.066h	51.513ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.720m	50.311ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.753m	10.800ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.018h	46.152ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.586m	31.000ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.363m	3.138ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.341m	3.192ms	1	1	100.00
		rom_volatile_raw_unlock	1.427m	2.170ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.284m	17.320ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.916m	19.368ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.587m	5.992ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.587m	5.992ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.587m	5.992ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.402m	3.488ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.774m	15.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.402m	3.488ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.732m	3.525ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.064m	3.754ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.774m	15.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.402m	3.488ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.691m	10.509ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.732m	3.525ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.064m	3.754ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.472m	4.821ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.320m	3.343ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.500m	3.656ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.658m	7.911ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.072m	6.458ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.112m	5.945ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.788m	11.721ms	1	1	100.00
		chip_prim_tl_access	1.289m	4.304ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.289m	4.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.301m	9.376ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.945m	8.325ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.680m	25.259ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.732m	7.044ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.310m	8.596ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.556m	6.555ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.785m	20.435ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.252m	16.978ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.541m	7.759ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.625m	10.008ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.633m	4.870ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.945m	8.325ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.452m	5.560ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.295m	32.979ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.202m	7.372ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.001m	5.435ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.817m	23.234ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.459m	7.663ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.574m	9.544ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	30.474m	30.251ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.518m	2.901ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.848m	9.053ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.848m	9.053ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.574m	9.544ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.817m	23.234ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.633m	4.870ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.564m	5.962ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.371m	3.128ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.287m	4.246ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.278m	5.061ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.127m	13.070ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.682m	3.283ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.136m	8.149ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.741m	4.828ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.387m	4.748ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.006m	2.917ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.064m	3.754ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.287m	4.246ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.287m	4.246ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	17.666m	18.169ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.217m	13.133ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.371m	3.128ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.023m	3.618ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.474m	5.890ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.319m	3.776ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.067m	13.927ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.409m	5.463ms	1	1	100.00
		chip_plic_all_irqs_10	4.718m	3.388ms	1	1	100.00
		chip_plic_all_irqs_20	5.092m	4.277ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.596m	2.961ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.218m	2.355ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.034m	15.249ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.095m	7.716ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.525m	2.616ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.510m	3.588ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.148m	3.159ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.732m	3.525ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.833m	4.825ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.600m	6.787ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.937m	8.383ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.214m	8.889ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.770m	5.651ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.459m	7.663ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.088m	25.182ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.829m	2.918ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.392m	3.287ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.411m	4.294ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.088m	25.182ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.088m	25.182ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	36.578m	20.904ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	36.578m	20.904ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.101m	6.166ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.021m	18.036ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.195m	3.251ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.039m	2.888ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.151m	3.427ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.092m	3.563ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.169m	8.323ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.219h	31.975ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.500m	11.972ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.735m	2.910ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.846m	2.486ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.687m	2.914ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.439h	71.126ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.104m	3.589ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.758m	10.984ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.854m	11.536ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.615m	11.882ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.880m	3.962ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.141m	3.787ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.497m	3.807ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.091s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.968m	5.414ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.816m	2.971ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.719m	4.688ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	10.373m	5.712ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.400m	2.665ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.472m	5.219ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.764m	2.492ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.968m	5.396ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.027m	6.071ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.205m	5.777ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.574m	9.544ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.758m	10.984ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.854m	11.536ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.615m	11.882ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.527m	5.250ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.299m	5.367ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.403h	37.999ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.403h	37.999ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.858m	3.310ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.790m	4.405ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	45.956m	19.273ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.498m	3.756ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.225m	4.864ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.426m	3.294ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.594m	2.949ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.347m	3.666ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.963s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.098m	2.962ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3188243763678998595913422842918321802315035645536797445782137683930741233342
    Line 619, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.36592356759401881323770672636992643814465885439710776120595788152020670637517
    Line 741, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.97592406525411653625902292004242136971234177980292642711839654856651089545189
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.83446308881254174782489140651375190451288711171686968807274929706587825504010
    Line 680, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.100858082174096867049333995047597152040022956765843997052684271943387797187654
    Line 710, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.109766720232211137675611382931070177703086760655013663125489271714704169453151
    Line 626, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.78197921264275889326592019046946310182760673789875119939498015196704922297974
    Line 620, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.94597056182295930335873764888980402279055703134908243799781651138010702850848
    Line 640, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.102082114124905495151473294800309629947688898437279484916873420797252542987944
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.94417959729790804605032948696599664209565251501768343366985739805301177345640
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.67629051124133054764917302194967834278869403903750153097196778558167265347359
    Line 623, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.86379679891460950353846719144238074914024819627037117115848200461358334023388
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.19711445069771656197312932831840600978339655598571616204272619088535675033941
    Line 653, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.65371169183862738648052910832788032009447168590000852233545577650498628623922
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.989s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.100436178323391555561527861325697629746333430743077912950373207786485161760193
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.482s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.40578492965073187320733761751444019022745194205797383430373760442776139288623
    Line 759, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.111533381212326861049033550135374341437421826573886415291859430238712959313489
    Line 608, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.43380983268409920171664662626005946643958727276661397378825768645273399839405
    Line 789, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.85987294026648307837377224982213162393254810294219232413192987370188667434095
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12762312393651174838677585397547792532440627181477586710296781123456365512499
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2615.697986 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2615.697986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@118429) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.74447847511415522692143179736534696669470578625956871030935914559830536445259
Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4245.686104 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@118429) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4245.686104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.63831982661415785905891498326487476742727877424443205190156301869896142163800
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3421.969384 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3421.969384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.29993642182984021205949083990859858849547919370175559753976204081689416331167
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2739.829134 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2739.829134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.42411668746762410314828713314842666087943198106305638820162385697162871082889
    Line 432, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2644.332096 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2644.332096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32265) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.70317074929252805926745320248235755212698627293571844155923605017911776779334
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2508.484080 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32265) { a_addr: 'h10620  a_data: 'h6966c177  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h4  a_user: 'h18628  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2508.484080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.45495896831383542439715797117464435894678844405240725632487124519003193882618
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2913.503962 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2913.503962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.75940995831361391574097761555271103294613010060079731533617901972528421685578
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3227.200000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3227.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.31131853108897100414164044322581512915682095300303773481280831140103159505948
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3429.621000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3429.621000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.112949367302551188122049955530481099503206886835515508447553272881695339925722
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22458.117094 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22458.117094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.51186088846288085930174838598675469782675449192565831361744525239094147675302
    Line 474, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3589.239312 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3589.239312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.73326571983648743557127364239501188519058485069617248443959156088917660929483
    Line 692, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1047047063871469453414786539000603462807153985277795490077442641914836096793
    Line 709, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32811) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.100601979049017893685400280830497444781146397170151497305095417701245517329430
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2264.626800 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32811) { a_addr: 'h107e4  a_data: 'h70459c58  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h19580  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2264.626800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---