ADC_CTRL Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	2.210s	5.941ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.060s	1.179ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.770s	442.721us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.186m	51.492ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.860s	844.501us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.040s	575.643us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.770s	442.721us	1	1	100.00
		adc_ctrl_csr_aliasing	3.860s	844.501us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	14.527m	486.678ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.145m	325.480ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.847m	160.488ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.414m	324.371ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.789m	352.694ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.455m	201.943ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.749m	600.000ms	0	1	0.00
V2	clock_gating	adc_ctrl_clock_gating	2.014m	334.200ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.600s	3.906ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.260m	43.542ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.400m	107.714ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.585m	322.989ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.760s	429.955us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.030s	434.529us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.480s	1.431ms	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.480s	1.431ms	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.060s	1.179ms	1	1	100.00
		adc_ctrl_csr_rw	2.770s	442.721us	1	1	100.00
		adc_ctrl_csr_aliasing	3.860s	844.501us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.300s	4.206ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.060s	1.179ms	1	1	100.00
		adc_ctrl_csr_rw	2.770s	442.721us	1	1	100.00
		adc_ctrl_csr_aliasing	3.860s	844.501us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.300s	4.206ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	7.440s	4.101ms	1	1	100.00
		adc_ctrl_tl_intg_err	10.150s	8.384ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	10.150s	8.384ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.430s	3.407ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.18093216751046331686678448101844379025615900807880655796735877011179036071933
      Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---