EDN Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.780s 14.889us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.560s 47.052us 1 1 100.00
V1 csr_rw edn_csr_rw 1.670s 14.680us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.240s 231.267us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.050s 70.420us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.720s 58.779us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.670s 14.680us 1 1 100.00
edn_csr_aliasing 2.050s 70.420us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.310s 69.224us 1 1 100.00
V2 csrng_commands edn_genbits 2.310s 69.224us 1 1 100.00
V2 genbits edn_genbits 2.310s 69.224us 1 1 100.00
V2 interrupts edn_intr 1.890s 23.769us 1 1 100.00
V2 alerts edn_alert 2.160s 43.219us 1 1 100.00
V2 errs edn_err 1.750s 80.919us 1 1 100.00
V2 disable edn_disable 1.670s 12.027us 1 1 100.00
edn_disable_auto_req_mode 1.880s 126.856us 1 1 100.00
V2 stress_all edn_stress_all 3.660s 665.947us 1 1 100.00
V2 intr_test edn_intr_test 1.600s 17.579us 1 1 100.00
V2 alert_test edn_alert_test 1.960s 27.410us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.710s 208.776us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.710s 208.776us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.560s 47.052us 1 1 100.00
edn_csr_rw 1.670s 14.680us 1 1 100.00
edn_csr_aliasing 2.050s 70.420us 1 1 100.00
edn_same_csr_outstanding 1.880s 19.848us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.560s 47.052us 1 1 100.00
edn_csr_rw 1.670s 14.680us 1 1 100.00
edn_csr_aliasing 2.050s 70.420us 1 1 100.00
edn_same_csr_outstanding 1.880s 19.848us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.380s 1.058ms 1 1 100.00
edn_tl_intg_err 2.720s 85.650us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.760s 28.647us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.160s 43.219us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.380s 1.058ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.380s 1.058ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.380s 1.058ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.380s 1.058ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.160s 43.219us 1 1 100.00
edn_sec_cm 4.380s 1.058ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.160s 43.219us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.720s 85.650us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets