47374bd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 5.000s | 24.426us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 5.000s | 41.283us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 5.000s | 100.401us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 9.000s | 1.626ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 5.000s | 297.699us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 128.248us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 5.000s | 100.401us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 5.000s | 297.699us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 5.000s | 24.426us | 1 | 1 | 100.00 |
| entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 4.000s | 4.447us | 0 | 1 | 0.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 4.000s | 4.447us | 0 | 1 | 0.00 |
| V2 | rng_mode | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 22.000s | 2.463ms | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| entropy_src_intr | 8.000s | 952.091us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 66.032us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 5.600m | 20.146ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 5.000s | 101.902us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 4.000s | 94.010us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 61.289us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 6.000s | 51.784us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 6.000s | 51.784us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 5.000s | 41.283us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 100.401us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 5.000s | 297.699us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 22.184us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 5.000s | 41.283us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 100.401us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 5.000s | 297.699us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 22.184us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 12 | 75.00 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 91.189us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 5.000s | 258.274us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 4.000s | 65.685us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 4.000s | 4.447us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 91.189us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 91.189us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 9.000s | 1.095ms | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 91.189us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 91.189us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 154.317us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 66.032us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 5.000s | 258.274us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 7.000s | 618.481us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 18 | 22 | 81.82 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 3 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.39174287837797385255296594796346300567730109969634760604575876149141106822931
Line 308, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
UVM_ERROR @ 1095450860 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 1095450860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_max_rate has 1 failures.
0.entropy_src_rng_max_rate.77430846208178685556138256808900316204153786969759664784655765873578805612894
Line 613, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 2462980690 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 2462980690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.31336400281746464181762282086214540882748153180783806591254399000314793298181
Line 259, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 618480867 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 618480867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,294): Assertion conf_rd_A has failed has 1 failures:
0.entropy_src_fw_ov.111795499148324105172181903314273311556320690269228965902655504963332769773053
Line 153, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,294): (time 4447497 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 4447497 ps: (entropy_src_csr_assert_fpv.sv:294) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 4447497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---