HMAC Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.190s 2.888ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.820s 26.296us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.580s 20.779us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.020s 548.529us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.350s 618.445us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.280s 150.162us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.580s 20.779us 1 1 100.00
hmac_csr_aliasing 6.350s 618.445us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.660s 6.751ms 1 1 100.00
V2 back_pressure hmac_back_pressure 13.840s 354.253us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.900s 162.282us 1 1 100.00
hmac_test_sha384_vectors 19.740s 279.724us 1 1 100.00
hmac_test_sha512_vectors 19.410s 2.797ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 972.946us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1.202ms 1 1 100.00
hmac_test_hmac512_vectors 11.360s 1.377ms 1 1 100.00
V2 burst_wr hmac_burst_wr 2.980s 58.815us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 11.432m 4.987ms 1 1 100.00
V2 error hmac_error 6.120s 835.049us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.482m 31.193ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.190s 2.888ms 1 1 100.00
hmac_long_msg 39.660s 6.751ms 1 1 100.00
hmac_back_pressure 13.840s 354.253us 1 1 100.00
hmac_datapath_stress 11.432m 4.987ms 1 1 100.00
hmac_burst_wr 2.980s 58.815us 1 1 100.00
hmac_stress_all 1.158m 24.588ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.190s 2.888ms 1 1 100.00
hmac_long_msg 39.660s 6.751ms 1 1 100.00
hmac_back_pressure 13.840s 354.253us 1 1 100.00
hmac_datapath_stress 11.432m 4.987ms 1 1 100.00
hmac_wipe_secret 1.482m 31.193ms 1 1 100.00
hmac_test_sha256_vectors 8.900s 162.282us 1 1 100.00
hmac_test_sha384_vectors 19.740s 279.724us 1 1 100.00
hmac_test_sha512_vectors 19.410s 2.797ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 972.946us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1.202ms 1 1 100.00
hmac_test_hmac512_vectors 11.360s 1.377ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.190s 2.888ms 1 1 100.00
hmac_long_msg 39.660s 6.751ms 1 1 100.00
hmac_back_pressure 13.840s 354.253us 1 1 100.00
hmac_datapath_stress 11.432m 4.987ms 1 1 100.00
hmac_burst_wr 2.980s 58.815us 1 1 100.00
hmac_error 6.120s 835.049us 1 1 100.00
hmac_wipe_secret 1.482m 31.193ms 1 1 100.00
hmac_test_sha256_vectors 8.900s 162.282us 1 1 100.00
hmac_test_sha384_vectors 19.740s 279.724us 1 1 100.00
hmac_test_sha512_vectors 19.410s 2.797ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 972.946us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1.202ms 1 1 100.00
hmac_test_hmac512_vectors 11.360s 1.377ms 1 1 100.00
hmac_stress_all 1.158m 24.588ms 1 1 100.00
V2 stress_all hmac_stress_all 1.158m 24.588ms 1 1 100.00
V2 alert_test hmac_alert_test 1.410s 40.915us 1 1 100.00
V2 intr_test hmac_intr_test 1.580s 11.922us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.310s 110.453us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.310s 110.453us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.820s 26.296us 1 1 100.00
hmac_csr_rw 1.580s 20.779us 1 1 100.00
hmac_csr_aliasing 6.350s 618.445us 1 1 100.00
hmac_same_csr_outstanding 2.450s 414.212us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.820s 26.296us 1 1 100.00
hmac_csr_rw 1.580s 20.779us 1 1 100.00
hmac_csr_aliasing 6.350s 618.445us 1 1 100.00
hmac_same_csr_outstanding 2.450s 414.212us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.090s 259.429us 1 1 100.00
hmac_tl_intg_err 2.280s 112.504us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.280s 112.504us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.190s 2.888ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.920s 111.827us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 6.654m 28.854ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.830s 13.324us 1 1 100.00
TOTAL 28 28 100.00