I2C Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: `47374bd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.850s	1.438ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	30.480s	2.646ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	29.556us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.750s	58.129us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.890s	746.079us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.050s	129.234us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.240s	54.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.750s	58.129us	1	1	100.00
		i2c_csr_aliasing	2.050s	129.234us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.430s	165.450us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.652m	50.017ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	23.490s	2.725ms	1	1	100.00
V2	host_override	i2c_host_override	1.570s	25.823us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.346m	9.658ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.085m	23.572ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.000s	425.984us	1	1	100.00
		i2c_host_fifo_fmt_empty	8.050s	1.252ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.440s	888.178us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	31.490s	7.243ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.860s	2.336ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.950s	97.154us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.890s	4.361ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.616m	56.509ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.360s	1.463ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	56.740s	8.028ms	1	1	100.00
		i2c_target_intr_smoke	5.320s	1.817ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.070s	158.577us	1	1	100.00
		i2c_target_fifo_reset_tx	2.130s	166.038us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.120m	49.101ms	1	1	100.00
		i2c_target_stress_rd	56.740s	8.028ms	1	1	100.00
		i2c_target_intr_stress_wr	16.870s	5.499ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.120s	3.199ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	29.990s	2.692ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.990s	826.160us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.550s	10.847ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.140s	1.972ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.360s	147.104us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	23.490s	2.725ms	1	1	100.00
		i2c_host_perf_precise	2.470s	74.224us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.860s	2.336ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.030s	57.836us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.170s	2.186ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.740s	1.988ms	1	1	100.00
		i2c_target_nack_txstretch	1.950s	159.598us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.600s	3.798ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.440s	904.477us	1	1	100.00
V2	alert_test	i2c_alert_test	1.510s	15.837us	1	1	100.00
V2	intr_test	i2c_intr_test	1.570s	19.308us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.980s	42.258us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.980s	42.258us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	29.556us	1	1	100.00
		i2c_csr_rw	1.750s	58.129us	1	1	100.00
		i2c_csr_aliasing	2.050s	129.234us	1	1	100.00
		i2c_same_csr_outstanding	1.870s	189.934us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	29.556us	1	1	100.00
		i2c_csr_rw	1.750s	58.129us	1	1	100.00
		i2c_csr_aliasing	2.050s	129.234us	1	1	100.00
		i2c_same_csr_outstanding	1.870s	189.934us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	1.960s	208.695us	1	1	100.00
		i2c_sec_cm	1.670s	356.681us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.960s	208.695us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.810s	692.921us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.870s	51.366us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.060s	33.463us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.29273114990085891024011580622315734415147593163092000973981194734713570408480
Line 202, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 50017114930 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3782434

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.16237381954948554387063783416689909984838415887493667134325952520249186808200
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  51366016 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  51366016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.97942967505706163831535158684335171531054684044478748087150398805476923328164
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10846895115 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10846895115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.73712999217271417950703522360057031163212456981309317666571158715911619389170
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 692921450 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 692921450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.17084029416408321745058639023309441481949221827414366973941768313025931490247
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  33462570 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (140 [0x8c] vs 0 [0x0])
  UVM_INFO @  33462570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```