KEYMGR Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.280s	101.885us	1	1	100.00
V1	random	keymgr_random	6.350s	1.425ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.030s	119.662us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	32.267us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.910s	3.725ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.420s	777.430us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.060s	192.353us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	32.267us	1	1	100.00
		keymgr_csr_aliasing	5.420s	777.430us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.410s	90.030us	1	1	100.00
V2	sideload	keymgr_sideload	3.520s	225.027us	1	1	100.00
		keymgr_sideload_kmac	5.490s	255.353us	1	1	100.00
		keymgr_sideload_aes	3.580s	315.754us	1	1	100.00
		keymgr_sideload_otbn	3.260s	254.261us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.680s	94.390us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.160s	209.358us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.800s	79.587us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	9.890s	1.178ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.890s	52.726us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.400s	167.164us	1	1	100.00
V2	stress_all	keymgr_stress_all	16.650s	2.340ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.620s	20.071us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.560s	22.292us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.540s	479.764us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.540s	479.764us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.030s	119.662us	1	1	100.00
		keymgr_csr_rw	1.640s	32.267us	1	1	100.00
		keymgr_csr_aliasing	5.420s	777.430us	1	1	100.00
		keymgr_same_csr_outstanding	2.200s	49.810us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.030s	119.662us	1	1	100.00
		keymgr_csr_rw	1.640s	32.267us	1	1	100.00
		keymgr_csr_aliasing	5.420s	777.430us	1	1	100.00
		keymgr_same_csr_outstanding	2.200s	49.810us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
		keymgr_tl_intg_err	5.250s	216.742us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.850s	193.848us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.850s	193.848us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.850s	193.848us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.850s	193.848us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.650s	21.803us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.250s	216.742us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.850s	193.848us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.410s	90.030us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.350s	1.425ms	1	1	100.00
		keymgr_csr_rw	1.640s	32.267us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.350s	1.425ms	1	1	100.00
		keymgr_csr_rw	1.640s	32.267us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.350s	1.425ms	1	1	100.00
		keymgr_csr_rw	1.640s	32.267us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.160s	209.358us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.890s	52.726us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.890s	52.726us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.350s	1.425ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.890s	522.898us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.100s	252.141us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.160s	209.358us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.100s	252.141us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.100s	252.141us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.100s	252.141us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.450s	1.171ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.100s	252.141us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.210s	429.510us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.48601260998240084358456728322089735198269521806382801095194797165191155174222
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @  21802738 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @  21802738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---