KMAC/UNMASKED Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.050s	725.597us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.860s	64.145us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.680s	14.838us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.930s	1.855ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.840s	483.486us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	61.765us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.680s	14.838us	1	1	100.00
		kmac_csr_aliasing	3.840s	483.486us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.590s	31.926us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	18.850us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.206m	487.828ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.769m	13.212ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.390s	616.526us	1	1	100.00
		kmac_test_vectors_sha3_256	22.500s	831.785us	1	1	100.00
		kmac_test_vectors_sha3_384	20.060m	69.270ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.879m	106.410ms	1	1	100.00
		kmac_test_vectors_shake_128	2.105m	17.833ms	1	1	100.00
		kmac_test_vectors_shake_256	3.481m	38.859ms	1	1	100.00
		kmac_test_vectors_kmac	2.310s	91.041us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.560s	97.188us	1	1	100.00
V2	sideload	kmac_sideload	20.310s	434.320us	1	1	100.00
V2	app	kmac_app	2.511m	36.925ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	56.120s	2.931ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.704m	76.710ms	1	1	100.00
V2	error	kmac_error	4.091m	64.030ms	1	1	100.00
V2	key_error	kmac_key_error	6.690s	3.787ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	14.270s	10.428ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.360s	6.065ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	28.150s	14.617ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	47.240s	37.676ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.320s	51.464us	1	1	100.00
V2	stress_all	kmac_stress_all	7.354m	114.012ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	17.422us	1	1	100.00
V2	alert_test	kmac_alert_test	1.570s	67.983us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.070s	520.731us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.070s	520.731us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.860s	64.145us	1	1	100.00
		kmac_csr_rw	1.680s	14.838us	1	1	100.00
		kmac_csr_aliasing	3.840s	483.486us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	435.943us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.860s	64.145us	1	1	100.00
		kmac_csr_rw	1.680s	14.838us	1	1	100.00
		kmac_csr_aliasing	3.840s	483.486us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	435.943us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.240s	404.219us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.240s	404.219us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.240s	404.219us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.240s	404.219us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	364.189us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	25.570s	8.842ms	1	1	100.00
		kmac_tl_intg_err	1.730s	23.379us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.730s	23.379us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.320s	51.464us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.050s	725.597us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	20.310s	434.320us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.240s	404.219us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.570s	8.842ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.570s	8.842ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.570s	8.842ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.050s	725.597us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.320s	51.464us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.570s	8.842ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.842m	45.046ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.050s	725.597us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	27.500s	1.880ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.105538870251477923111788205979986691038297906584837934818224120273716905171199
      Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10428086049 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x15dbb000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10428086049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:924) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.57669704627501679049104040001143799661831673166439734968756398008179311840375
      Line 106, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1879977591 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1879977591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.113495573805560476157443945924038785012402580136861812521618224293183097703364
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  23379325 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  23379325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---