OTBN Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	40.000s	172.577us	1	1	100.00
V1	single_binary	otbn_single	10.000s	150.039us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	22.534us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	27.981us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	54.370us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	31.637us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	102.395us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	27.981us	1	1	100.00
		otbn_csr_aliasing	6.000s	31.637us	1	1	100.00
V1	mem_walk	otbn_mem_walk	22.000s	712.092us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	735.984us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	23.000s	318.954us	1	1	100.00
V2	multi_error	otbn_multi_err	45.000s	339.643us	1	1	100.00
V2	back_to_back	otbn_multi	50.000s	890.999us	1	1	100.00
V2	stress_all	otbn_stress_all	51.000s	378.003us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	37.051us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	17.000s	74.939us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	30.659us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	41.816us	1	1	100.00
V2	intr_test	otbn_intr_test	35.000s	18.598us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	45.000s	219.110us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	45.000s	219.110us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	22.534us	1	1	100.00
		otbn_csr_rw	7.000s	27.981us	1	1	100.00
		otbn_csr_aliasing	6.000s	31.637us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	20.711us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	22.534us	1	1	100.00
		otbn_csr_rw	7.000s	27.981us	1	1	100.00
		otbn_csr_aliasing	6.000s	31.637us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	20.711us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	56.664us	1	1	100.00
		otbn_dmem_err	8.000s	43.570us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	25.751us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	108.814us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	529.906us	1	1	100.00
		otbn_urnd_err	9.000s	57.146us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	11.579us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	20.972us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	29.403us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	5.000s	1.837us	0	1	0.00
		otbn_tl_intg_err	59.000s	147.242us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	331.671us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	40.000s	172.577us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	43.570us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	56.664us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	59.000s	147.242us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	37.051us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	56.664us	1	1	100.00
		otbn_dmem_err	8.000s	43.570us	1	1	100.00
		otbn_zero_state_err_urnd	17.000s	74.939us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	11.579us	1	1	100.00
		otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	56.664us	1	1	100.00
		otbn_dmem_err	8.000s	43.570us	1	1	100.00
		otbn_zero_state_err_urnd	17.000s	74.939us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	11.579us	1	1	100.00
		otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	37.051us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	56.664us	1	1	100.00
		otbn_dmem_err	8.000s	43.570us	1	1	100.00
		otbn_zero_state_err_urnd	17.000s	74.939us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	11.579us	1	1	100.00
		otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	62.665us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	21.001us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	21.000s	79.030us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	21.000s	79.030us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	63.857us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	191.899us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	139.169us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	139.169us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	24.187us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	50.000s	890.999us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	20.224us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	150.039us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.000s	1.837us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.367m	3.508ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:925) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.40241746379872290194655077154160199192478142161182645873102949666087481904543
      Line 205, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3508129330 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3508129330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.8331027302545615869661213438230325514284446239419081932888322523353703127660
      Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 1837483 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1837483 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @   1837483 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @   1837483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---