PATTGEN Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	15.000s	40.722us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	27.952us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	19.556us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	639.070us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	316.361us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	30.942us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	19.556us	1	1	100.00
		pattgen_csr_aliasing	4.000s	316.361us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	46.000s	1.345ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	14.000s	542.916us	1	1	100.00
V2	error	pattgen_error	14.000s	16.799us	1	1	100.00
V2	stress_all	pattgen_stress_all	10.000s	69.660us	1	1	100.00
V2	alert_test	pattgen_alert_test	8.000s	12.531us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	22.953us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	196.785us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	196.785us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	27.952us	1	1	100.00
		pattgen_csr_rw	4.000s	19.556us	1	1	100.00
		pattgen_csr_aliasing	4.000s	316.361us	1	1	100.00
		pattgen_same_csr_outstanding	5.000s	119.730us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	27.952us	1	1	100.00
		pattgen_csr_rw	4.000s	19.556us	1	1	100.00
		pattgen_csr_aliasing	4.000s	316.361us	1	1	100.00
		pattgen_same_csr_outstanding	5.000s	119.730us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	52.103us	1	1	100.00
		pattgen_sec_cm	12.000s	130.858us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	52.103us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	20.000s	2.813ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	13.000s	31.673us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:925) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.22872038250352405906965618862845931323147206631974695673711245733670584569858
      Line 163, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 343292182 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 343297046 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 343297046 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 343501126 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]