ROM_CTRL/32KB Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.440s 144.727us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.360s 389.430us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.030s 130.876us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.850s 290.978us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.800s 288.836us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.570s 184.130us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.030s 130.876us 1 1 100.00
rom_ctrl_csr_aliasing 4.800s 288.836us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.330s 655.264us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.280s 130.103us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.700s 192.980us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.110s 3.411ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.740s 386.506us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.150s 126.422us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.790s 538.879us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.790s 538.879us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.360s 389.430us 1 1 100.00
rom_ctrl_csr_rw 5.030s 130.876us 1 1 100.00
rom_ctrl_csr_aliasing 4.800s 288.836us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 371.945us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.360s 389.430us 1 1 100.00
rom_ctrl_csr_rw 5.030s 130.876us 1 1 100.00
rom_ctrl_csr_aliasing 4.800s 288.836us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 371.945us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.540s 3.585ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
rom_ctrl_tl_intg_err 42.250s 381.653us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.440s 144.727us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.440s 144.727us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.440s 144.727us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 42.250s 381.653us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.740s 386.506us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 57.140s 4.120ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.540s 3.585ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.496m 3.796ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.200m 6.622ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00