ROM_CTRL/64KB Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.260s 223.648us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.960s 570.942us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.270s 299.988us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.290s 292.166us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.950s 296.997us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.940s 1.077ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.270s 299.988us 1 1 100.00
rom_ctrl_csr_aliasing 6.950s 296.997us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.620s 304.549us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.930s 212.150us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 10.390s 1.069ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 18.700s 1.114ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.030s 1.424ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.130s 295.484us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.030s 1.275ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.030s 1.275ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.960s 570.942us 1 1 100.00
rom_ctrl_csr_rw 7.270s 299.988us 1 1 100.00
rom_ctrl_csr_aliasing 6.950s 296.997us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.510s 1.538ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.960s 570.942us 1 1 100.00
rom_ctrl_csr_rw 7.270s 299.988us 1 1 100.00
rom_ctrl_csr_aliasing 6.950s 296.997us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.510s 1.538ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 35.580s 6.367ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
rom_ctrl_tl_intg_err 35.510s 1.518ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.260s 223.648us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.260s 223.648us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.260s 223.648us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 35.510s 1.518ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.030s 1.424ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.206m 11.592ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 35.580s 6.367ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.501m 2.072ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.617m 4.206ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00