RV_TIMER Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	17.870s	280.837ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.490s	19.768us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.400s	40.909us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.640s	222.680us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.600s	22.309us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.830s	18.260us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.400s	40.909us	1	1	100.00
		rv_timer_csr_aliasing	1.600s	22.309us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	11.273m	50.246ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.957m	422.031ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	10.400m	524.312ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	10.400m	524.312ms	1	1	100.00
V2	stress	rv_timer_stress_all	4.484m	520.838ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.730s	46.745us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.430s	38.631us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.430s	38.631us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.490s	19.768us	1	1	100.00
		rv_timer_csr_rw	1.400s	40.909us	1	1	100.00
		rv_timer_csr_aliasing	1.600s	22.309us	1	1	100.00
		rv_timer_same_csr_outstanding	1.920s	35.065us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.490s	19.768us	1	1	100.00
		rv_timer_csr_rw	1.400s	40.909us	1	1	100.00
		rv_timer_csr_aliasing	1.600s	22.309us	1	1	100.00
		rv_timer_same_csr_outstanding	1.920s	35.065us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.040s	108.445us	1	1	100.00
		rv_timer_tl_intg_err	1.720s	336.410us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.720s	336.410us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	15.490s	6.222ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.72406431774223675403518833027543765131442518399406784528068052138138685434857
      Line 159, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6222267316 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6222267316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---