SPI_DEVICE/1R1W Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.742m	24.284ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.080s	325.600us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.440s	106.733us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.720s	2.488ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.590s	908.867us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	77.703us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.440s	106.733us	1	1	100.00
		spi_device_csr_aliasing	15.590s	908.867us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.510s	12.095us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	194.718us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.710s	29.879us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	1.176us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.570s	1.982us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.390s	622.955us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.390s	622.955us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.370s	3.416ms	1	1	100.00
		spi_device_tpm_sts_read	1.730s	259.588us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.310s	4.665ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.570s	1.068ms	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	21.900s	47.685ms	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	21.900s	47.685ms	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.450s	198.893us	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.450s	198.893us	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.450s	198.893us	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.450s	198.893us	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.450s	198.893us	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	11.930s	17.756ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.080s	2.731ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.080s	2.731ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.080s	2.731ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.550s	726.779us	1	1	100.00
		spi_device_read_buffer_direct	4.110s	550.900us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.080s	2.731ms	1	1	100.00
		spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	50.410s	10.912ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.310s	578.055us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.310s	578.055us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.742m	24.284ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.611m	151.910ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.700s	44.921us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.470s	37.364us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.670s	48.456us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.650s	135.572us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.650s	135.572us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.080s	325.600us	1	1	100.00
		spi_device_csr_rw	3.440s	106.733us	1	1	100.00
		spi_device_csr_aliasing	15.590s	908.867us	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	210.044us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.080s	325.600us	1	1	100.00
		spi_device_csr_rw	3.440s	106.733us	1	1	100.00
		spi_device_csr_aliasing	15.590s	908.867us	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	210.044us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.930s	121.747us	1	1	100.00
		spi_device_tl_intg_err	5.900s	116.933us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.900s	116.933us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.676m	39.406ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.104852607989659400994087252268073677304646700179972600824824376059370320263676
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    988900 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[0])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    988900 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    988900 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[896])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.86235132797792292052331420938947614791677511076749386580185969085849469383076
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1101891 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1101891 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1153891 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x368f92 [1101101000111110010010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1153891 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x368f92 [1101101000111110010010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])