SPI_DEVICE/2P Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	55.540s	39.376ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.300s	50.945us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	437.989us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.300s	2.843ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.860s	3.062ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	185.684us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	437.989us	1	1	100.00
		spi_device_csr_aliasing	12.860s	3.062ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.600s	14.308us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.830s	28.623us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.290s	51.158us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.060s	94.971us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.790s	2.138us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.030s	41.291us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.030s	41.291us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.430s	3.843ms	1	1	100.00
		spi_device_tpm_sts_read	1.940s	14.873us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.040s	3.622ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.600s	120.702us	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.850s	1.453ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.850s	1.453ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.580s	4.373ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.580s	4.373ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.580s	4.373ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.580s	4.373ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.580s	4.373ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	10.810s	19.770ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	45.030s	7.641ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	45.030s	7.641ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	45.030s	7.641ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.580s	1.084ms	1	1	100.00
		spi_device_read_buffer_direct	7.130s	4.351ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	45.030s	7.641ms	1	1	100.00
		spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	38.690s	27.923ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.930s	71.997us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.930s	71.997us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	55.540s	39.376ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	59.060s	17.243ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.359m	37.242ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.520s	181.427us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.640s	16.793us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.260s	111.262us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.260s	111.262us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.300s	50.945us	1	1	100.00
		spi_device_csr_rw	2.880s	437.989us	1	1	100.00
		spi_device_csr_aliasing	12.860s	3.062ms	1	1	100.00
		spi_device_same_csr_outstanding	2.730s	689.406us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.300s	50.945us	1	1	100.00
		spi_device_csr_rw	2.880s	437.989us	1	1	100.00
		spi_device_csr_aliasing	12.860s	3.062ms	1	1	100.00
		spi_device_same_csr_outstanding	2.730s	689.406us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.350s	110.015us	1	1	100.00
		spi_device_tl_intg_err	6.400s	4.722ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.400s	4.722ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.230m	17.244ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.53845768823958380943307939813514360220541625188588465883258633089817739157956
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1397755 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1397755 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1437755 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x4b81bd [10010111000000110111101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1437755 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)