SPI_HOST Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	52.000s	4.228ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	55.844us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	16.451us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	65.481us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	212.112us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	21.100us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	16.451us	1	1	100.00
		spi_host_csr_aliasing	4.000s	212.112us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	16.285us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	118.980us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	100.872us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	317.682us	1	1	100.00
		spi_host_error_cmd	4.000s	17.533us	1	1	100.00
		spi_host_event	48.000s	4.752ms	1	1	100.00
V2	clock_rate	spi_host_speed	9.000s	1.698ms	1	1	100.00
V2	speed	spi_host_speed	9.000s	1.698ms	1	1	100.00
V2	chip_select_timing	spi_host_speed	9.000s	1.698ms	1	1	100.00
V2	sw_reset	spi_host_sw_reset	15.000s	1.295ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	581.563us	1	1	100.00
V2	cpol_cpha	spi_host_speed	9.000s	1.698ms	1	1	100.00
V2	full_cycle	spi_host_speed	9.000s	1.698ms	1	1	100.00
V2	duplex	spi_host_smoke	52.000s	4.228ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	52.000s	4.228ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	596.531us	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.010ms	1	1	100.00
V2	stall	spi_host_status_stall	54.000s	22.941ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	6.000s	613.333us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	317.682us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	50.902us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	20.969us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	576.577us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	576.577us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	55.844us	1	1	100.00
		spi_host_csr_rw	3.000s	16.451us	1	1	100.00
		spi_host_csr_aliasing	4.000s	212.112us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	24.647us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	55.844us	1	1	100.00
		spi_host_csr_rw	3.000s	16.451us	1	1	100.00
		spi_host_csr_aliasing	4.000s	212.112us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	24.647us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	403.218us	1	1	100.00
		spi_host_sec_cm	3.000s	582.375us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	403.218us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	49.517m	99.416ms	1	1	100.00
		TOTAL			26	26	100.00