SRAM_CTRL/MAIN Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.090s	4.075ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	15.520us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	29.794us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.720s	710.447us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.750s	49.828us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.170s	1.097ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	29.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	49.828us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.301m	24.625ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.032m	2.562ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.839m	25.617ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.314m	3.868ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.139m	75.685ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.854m	4.713ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.209m	31.963ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.327m	24.986ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.600s	1.353ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.088m	141.297ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.370s	3.159ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	30.220s	1.559ms	1	1	100.00
		sram_ctrl_throughput_w_readback	36.360s	1.698ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.783m	2.557ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.080s	382.141us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	30.070m	290.256ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	13.929us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.190s	391.439us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.190s	391.439us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	15.520us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	29.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	49.828us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	160.433us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	15.520us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	29.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	49.828us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	160.433us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.610s	28.375ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
		sram_ctrl_tl_intg_err	3.110s	181.727us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.110s	181.727us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.783m	2.557ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.783m	2.557ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	29.794us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.327m	24.986ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.327m	24.986ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.327m	24.986ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.209m	31.963ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.610s	2.925ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.610s	28.375ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.140s	2.997ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.090s	4.075ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.090s	4.075ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.327m	24.986ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.209m	31.963ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.090s	4.075ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.070s	59.950us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.055m	8.540ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.34150528353969804711611066500751353185596784503013916249985530430650307166271
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  59950056 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  59950056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---