SRAM_CTRL/RET Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.210s	263.029us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.720s	48.273us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	22.915us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.900s	92.532us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	16.346us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.450s	222.745us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	22.915us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	16.346us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.470s	228.602us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.420s	60.386us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.102m	7.032ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.732m	2.388ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	59.890s	4.496ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.530m	5.107ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.340s	1.176ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.219m	44.250ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.920s	100.102us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.405m	10.941ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.860s	89.160us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	42.270s	560.886us	1	1	100.00
		sram_ctrl_throughput_w_readback	7.220s	482.487us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.905m	466.741us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.920s	54.824us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	14.846m	34.527ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	37.421us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.520s	504.497us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.520s	504.497us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.720s	48.273us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	22.915us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	16.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	76.425us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.720s	48.273us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	22.915us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	16.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	76.425us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.080s	392.963us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
		sram_ctrl_tl_intg_err	2.550s	102.470us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.550s	102.470us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.905m	466.741us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.905m	466.741us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	22.915us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.219m	44.250ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.219m	44.250ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.219m	44.250ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.340s	1.176ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.620s	65.431us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.080s	392.963us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.050s	48.060us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.210s	263.029us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.210s	263.029us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.219m	44.250ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.340s	1.176ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.210s	263.029us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.460s	3.864us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.035m	1.014ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.33766100322971010105156202427106772918985227079997915608160243318163423688536
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  65431016 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  65431016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.43001894575877260822124666544580344099886785234976158368239380370234208136044
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3863894 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3863894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---