SYSRST_CTRL Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.490s 2.119ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.920s 2.462ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.530s 2.415ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.110s 2.337ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.140s 4.053ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.470s 2.096ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 36.250s 67.713ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 10.200s 3.300ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.780s 2.074ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.470s 2.096ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.200s 3.300ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.070m 148.665ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 3.384m 117.182ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.110s 4.060ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.870s 3.649ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.790s 2.535ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 5.290s 2.045ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.060s 3.565ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.690s 2.633ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 8.620s 15.343ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 17.470s 34.691ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 4.090s 6.184ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.360s 2.041ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.450s 2.027ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.560s 2.125ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.560s 2.125ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.140s 4.053ms 1 1 100.00
sysrst_ctrl_csr_rw 2.470s 2.096ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.200s 3.300ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.320s 10.855ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.140s 4.053ms 1 1 100.00
sysrst_ctrl_csr_rw 2.470s 2.096ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.200s 3.300ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.320s 10.855ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 25.070s 22.027ms 1 1 100.00
sysrst_ctrl_tl_intg_err 39.560s 42.535ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 39.560s 42.535ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 11.580s 4.875ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00