UART Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: 47374bd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	8.810s	5.687ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.490s	57.976us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.490s	41.160us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.470s	105.763us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.540s	27.938us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.570s	187.499us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.490s	41.160us	1	1	100.00
		uart_csr_aliasing	1.540s	27.938us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	29.780s	29.037ms	1	1	100.00
V2	parity	uart_smoke	8.810s	5.687ms	1	1	100.00
		uart_tx_rx	29.780s	29.037ms	1	1	100.00
V2	parity_error	uart_intr	5.232m	251.276ms	1	1	100.00
		uart_rx_parity_err	2.386m	113.802ms	1	1	100.00
V2	watermark	uart_tx_rx	29.780s	29.037ms	1	1	100.00
		uart_intr	5.232m	251.276ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.800s	66.806ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.702m	149.771ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	40.580s	121.680ms	1	1	100.00
V2	rx_frame_err	uart_intr	5.232m	251.276ms	1	1	100.00
V2	rx_break_err	uart_intr	5.232m	251.276ms	1	1	100.00
V2	rx_timeout	uart_intr	5.232m	251.276ms	1	1	100.00
V2	perf	uart_perf	4.956m	12.115ms	1	1	100.00
V2	sys_loopback	uart_loopback	26.490s	6.560ms	1	1	100.00
V2	line_loopback	uart_loopback	26.490s	6.560ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	21.710s	83.095ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.650s	4.711ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.590s	1.944ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.340s	6.864ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.694m	120.186ms	1	1	100.00
V2	stress_all	uart_stress_all	8.187m	221.882ms	1	1	100.00
V2	alert_test	uart_alert_test	1.490s	14.671us	1	1	100.00
V2	intr_test	uart_intr_test	1.520s	35.791us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	53.364us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	53.364us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.490s	57.976us	1	1	100.00
		uart_csr_rw	1.490s	41.160us	1	1	100.00
		uart_csr_aliasing	1.540s	27.938us	1	1	100.00
		uart_same_csr_outstanding	1.470s	50.157us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.490s	57.976us	1	1	100.00
		uart_csr_rw	1.490s	41.160us	1	1	100.00
		uart_csr_aliasing	1.540s	27.938us	1	1	100.00
		uart_same_csr_outstanding	1.470s	50.157us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.770s	77.897us	1	1	100.00
		uart_tl_intg_err	1.970s	95.187us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.970s	95.187us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.020s	4.129ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.35169544049822700916060485225801413311539498061770447608515672990836748056613
      Line 94, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2433244347 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2433259122 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2433259122 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 2433268157 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1