CHIP Simulation Results

Monday April 21 2025 18:31:29 UTC

GitHub Revision: `47374bd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.964m	3.223ms	1	1	100.00
		chip_sw_example_rom	1.093m	2.742ms	1	1	100.00
		chip_sw_example_manufacturer	2.457m	2.977ms	1	1	100.00
		chip_sw_example_concurrency	3.042m	3.068ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.912m	3.836ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.990m	4.913ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.706m	6.664ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.478m	32.133ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.102m	2.441ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.478m	32.133ms	1	1	100.00
		chip_csr_rw	2.990m	4.913ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.220s	46.038us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.060m	3.836ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.060m	3.836ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.060m	3.836ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.086m	4.386ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.086m	4.386ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.468m	3.927ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.960m	4.008ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.022m	4.100ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.630m	8.338ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.841m	3.960ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.218m	4.757ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.289m	5.336ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.289m	5.336ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.268m	2.665ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.045m	6.365ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.602m	3.009ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.923m	3.575ms	1	1	100.00
		chip_tap_straps_testunlock0	8.420m	8.981ms	1	1	100.00
		chip_tap_straps_rma	1.762m	2.723ms	1	1	100.00
		chip_tap_straps_prod	11.693m	11.956ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.216m	2.737ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.095m	8.986ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.167m	5.845ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.167m	5.845ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.717m	7.929ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.869m	21.592ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.035m	4.767ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.314m	6.287ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.605m	19.162ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.046m	3.436ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.318m	6.110ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.228m	3.130ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.952m	11.478ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.363m	3.548ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.813m	4.097ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.007m	2.716ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.569m	2.796ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.633m	6.980ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.743m	5.613ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.433m	3.581ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.743m	5.613ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.998m	2.519ms	1	1	100.00
		chip_sw_aes_smoketest	2.467m	2.974ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.473m	2.593ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.338m	2.188ms	1	1	100.00
		chip_sw_csrng_smoketest	1.880m	2.180ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.018m	3.518ms	1	1	100.00
		chip_sw_gpio_smoketest	2.953m	2.863ms	1	1	100.00
		chip_sw_hmac_smoketest	3.332m	2.977ms	1	1	100.00
		chip_sw_kmac_smoketest	3.272m	2.750ms	1	1	100.00
		chip_sw_otbn_smoketest	19.611m	12.020ms	0	1	0.00
		chip_sw_pwrmgr_smoketest	5.291m	5.412ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.692m	4.947ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.496m	3.048ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.287m	2.893ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.927m	2.274ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.254m	2.766ms	1	1	100.00
		chip_sw_uart_smoketest	2.919m	2.874ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.723m	3.280ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.826m	4.804ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.028h	61.028ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.253m	15.480ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.518m	6.091ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.663m	3.743ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.041m	2.793ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.852h	52.984ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.825h	55.328ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.638m	3.187ms	1	1	100.00
V2	tl_d_illegal_access	chip_tl_errors	1.638m	3.187ms	1	1	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.478m	32.133ms	1	1	100.00
		chip_same_csr_outstanding	49.117m	32.503ms	1	1	100.00
		chip_csr_hw_reset	1.912m	3.836ms	1	1	100.00
		chip_csr_rw	2.990m	4.913ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.478m	32.133ms	1	1	100.00
		chip_same_csr_outstanding	49.117m	32.503ms	1	1	100.00
		chip_csr_hw_reset	1.912m	3.836ms	1	1	100.00
		chip_csr_rw	2.990m	4.913ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	5.680s	60.964us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.480s	48.998us	1	1	100.00
		xbar_smoke_large_delays	1.002m	10.472ms	1	1	100.00
		xbar_smoke_slow_rsp	51.700s	6.020ms	1	1	100.00
		xbar_random_zero_delays	16.160s	292.068us	1	1	100.00
		xbar_random_large_delays	1.277m	12.652ms	1	1	100.00
		xbar_random_slow_rsp	4.144m	30.253ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	13.530s	199.301us	1	1	100.00
		xbar_error_and_unmapped_addr	9.220s	122.658us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	23.050s	1.255ms	1	1	100.00
		xbar_error_and_unmapped_addr	9.220s	122.658us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	41.890s	1.891ms	1	1	100.00
		xbar_access_same_device_slow_rsp	6.718m	48.631ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	9.670s	103.991us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.337m	9.870ms	1	1	100.00
		xbar_stress_all_with_error	2.678m	3.599ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.223m	3.530ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.086m	2.051ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.253m	15.480ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.056m	24.368ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.037m	14.610ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.578m	10.507ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.618m	16.354ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.508m	16.212ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.776m	15.437ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.034m	14.692ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.810s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	29.590s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	35.700s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.850s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.860s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.470s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.530s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.310s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.640s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.550s	10.160us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.390s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.410s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.450s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.860s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.960s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.940s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	28.300s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.800s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.470s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.670s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.030s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	27.160s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.030s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.710s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.550s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.324m	10.880ms	1	1	100.00
		rom_e2e_asm_init_dev	36.746m	15.542ms	1	1	100.00
		rom_e2e_asm_init_prod	38.722m	15.085ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.960m	15.462ms	1	1	100.00
		rom_e2e_asm_init_rma	35.769m	14.923ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.977m	15.283ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.363m	15.000ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.282m	14.785ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.698m	15.974ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3.791m	18.747ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3.791m	18.747ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.175m	3.455ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.046m	3.436ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.251m	3.457ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.415m	2.951ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	23.993m	10.705ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.997m	3.472ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.808m	4.929ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.776m	5.667ms	1	1	100.00
		chip_plic_all_irqs_10	4.632m	4.109ms	1	1	100.00
		chip_plic_all_irqs_20	5.205m	4.036ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.480m	3.085ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.367m	12.288ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.010m	4.832ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.430m	2.706ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.563m	10.736ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.392m	8.797ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	21.043m	9.590ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.084m	7.478ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.961h	255.313ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.859m	3.953ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.291m	5.412ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.859m	3.953ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.750m	7.085ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.750m	7.085ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.153m	7.183ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.047m	3.805ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.607m	6.349ms	1	1	100.00
		chip_sw_aes_idle	2.415m	2.951ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.306m	2.932ms	1	1	100.00
		chip_sw_kmac_idle	2.163m	2.665ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.421m	4.173ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.990m	3.786ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.510m	4.395ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.389m	4.767ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.938m	9.539ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.520m	3.228ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.314m	3.861ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.474m	4.063ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.230m	4.591ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.168m	3.532ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.265m	4.932ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.717m	7.929ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.802m	6.565ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.474m	4.063ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.230m	4.591ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.035m	4.767ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.314m	6.287ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.605m	19.162ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.046m	3.436ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.318m	6.110ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.228m	3.130ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.952m	11.478ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.363m	3.548ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.813m	4.097ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.007m	2.716ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.830m	2.892ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.470m	3.942ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.782m	6.902ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.114m	25.233ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.386m	2.937ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.263m	2.907ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	14.220m	9.853ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.383m	3.947ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.431m	5.647ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.021m	24.643ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	43.901m	25.294ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.717m	7.929ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.066m	5.034ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.889m	3.354ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	19.392m	8.797ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.806m	6.122ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.996m	2.750ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.332m	7.655ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.160m	3.339ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	59.404m	24.693ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.549m	2.578ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.100m	6.745ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.549m	2.578ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.806m	6.122ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.318m	2.531ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	24.021m	23.897ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.052m	6.047ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.314m	6.287ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.014m	3.993ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.035m	4.767ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.760m	42.967ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	24.021m	23.897ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.135m	3.501ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.760m	42.967ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.504m	10.878ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.300m	5.345ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.718m	5.728ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.718m	5.728ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.139m	2.817ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.228m	3.130ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.306m	2.932ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.437m	3.197ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	11.943m	6.798ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.570m	4.522ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.815m	4.516ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.500m	5.570ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.304m	3.821ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.952m	11.478ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.599m	7.887ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	23.993m	10.705ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.323m	11.522ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.187m	2.385ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.951m	2.888ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.363m	3.548ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.333m	2.735ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.849m	9.295ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.163m	2.665ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.808m	4.929ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.923m	3.575ms	1	1	100.00
		chip_tap_straps_rma	1.762m	2.723ms	1	1	100.00
		chip_tap_straps_prod	11.693m	11.956ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.923m	2.209ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.555m	7.219ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.446m	4.178ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.760m	42.967ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.179m	2.974ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.684m	5.655ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.572m	7.068ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.468m	7.277ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.694m	8.811ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.968m	8.026ms	1	1	100.00
		chip_prim_tl_access	4.504m	10.878ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.802m	6.565ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.520m	3.228ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.314m	3.861ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.474m	4.063ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.230m	4.591ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.168m	3.532ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.265m	4.932ms	1	1	100.00
		chip_tap_straps_dev	2.923m	3.575ms	1	1	100.00
		chip_tap_straps_rma	1.762m	2.723ms	1	1	100.00
		chip_tap_straps_prod	11.693m	11.956ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.934m	13.680ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.249m	2.710ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.323m	3.047ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.724m	2.923ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.396m	3.276ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.111m	28.830ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.934m	13.680ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.050h	50.523ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	56.443m	45.266ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.675m	8.177ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.344m	45.181ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.111m	28.830ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.413m	2.654ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.313m	2.585ms	1	1	100.00
		rom_volatile_raw_unlock	1.188m	2.741ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.661m	17.352ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.605m	19.162ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.607m	6.349ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.607m	6.349ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.607m	6.349ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.579m	4.186ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	24.021m	23.897ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.579m	4.186ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.475m	5.371ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.954m	2.574ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	24.021m	23.897ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.579m	4.186ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.369m	11.443ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.475m	5.371ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.954m	2.574ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.894m	4.802ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.923m	2.209ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.179m	2.974ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.684m	5.655ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.572m	7.068ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.468m	7.277ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.420m	5.583ms	1	1	100.00
		chip_prim_tl_access	4.504m	10.878ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.504m	10.878ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.367m	7.648ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.241m	9.711ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.161m	26.910ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.758m	7.344ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.268m	6.873ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.947m	7.638ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.002m	24.254ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.707m	16.663ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.750m	7.085ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.781m	11.430ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.183m	5.186ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.241m	9.711ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.105m	4.916ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.616m	34.021ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.550m	6.305ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.575m	4.432ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.096m	21.381ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.129m	7.640ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.982m	9.572ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.462m	20.923ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.122m	2.239ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.694m	8.811ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.694m	8.811ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.982m	9.572ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.096m	21.381ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.183m	5.186ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.291m	5.412ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.750m	3.880ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.451m	3.621ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.289m	4.534ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.367m	12.288ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.986m	2.788ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	21.043m	9.590ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.591m	5.038ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.426m	4.558ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.471m	2.933ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.954m	2.574ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.451m	3.621ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.451m	3.621ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.618m	4.186ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.091m	13.650ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.750m	3.880ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.543m	3.928ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.676m	6.913ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.762m	2.723ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.934m	13.680ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.776m	5.667ms	1	1	100.00
		chip_plic_all_irqs_10	4.632m	4.109ms	1	1	100.00
		chip_plic_all_irqs_20	5.205m	4.036ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.514m	2.399ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.162m	3.181ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.253m	15.480ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.920m	7.851ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.035m	3.461ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.064m	3.282ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.838m	2.822ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.475m	5.371ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.813m	4.097ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.400m	8.959ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.665m	7.337ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.968m	8.026ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.167m	5.845ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.129m	7.640ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.393m	25.321ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.779m	2.511ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.923m	3.437ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.104m	4.944ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.393m	25.321ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.393m	25.321ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.208m	21.050ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.208m	21.050ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.057m	5.815ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3.791m	18.747ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.401m	2.980ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.248m	3.121ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.850m	3.000ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.840m	4.091ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.698m	8.482ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.301h	31.661ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.104m	12.185ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.522m	3.523ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.741m	3.271ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.432m	2.400ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.343h	71.024ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.626m	3.877ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.133m	11.823ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.970m	11.267ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.036m	10.836ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.252m	4.115ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.731m	3.897ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.163m	3.691ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	24.268s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.981m	5.065ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.411m	2.468ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.169m	6.190ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.288m	7.385ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.231m	2.420ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.952m	5.241ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.062m	2.539ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.213m	4.974ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.049m	6.243ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.206m	4.757ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.982m	9.572ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.133m	11.823ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.970m	11.267ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.036m	10.836ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.796m	6.432ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.612m	5.342ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.342h	38.193ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.342h	38.193ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.598m	3.190ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.086m	4.386ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.969m	19.511ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.190m	2.580ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.897m	5.580ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.239m	2.997ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.427m	3.149ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.530m	4.149ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	19.815s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.071m	2.735ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.73394699024482129516353590986673222883444851647153768130728741451434919571303
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.48911936505796022040762007266118461546303926205647681959864034088635606123194
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.103031397561807061217632016064311094937896279509164662627772389659254472572198
    Line 715, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.78879533027525126627810130544485948220904239422585005113734834720049456071965
    Line 665, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.31355926018060056664126080957179740777722977080606291300427314114102025108231
    Line 741, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.53801171289307365618256324520705328129872083036779297560531654032590942391916
    Line 681, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.107828681735969404720424957957688111928451079876196856443097534795568039002250
    Line 668, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.9831261682154856292462671925528683824570988192281905636350365841764585238322
    Line 622, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1085737635933309122142326806628016844932841542845481898816538609497885042072
    Line 655, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.52026769869103658904627776048560171930173265530538731037060008434201884830124
    Line 624, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.77811073234587025710358133428972170235996541965271142574957306116010859880127
    Line 694, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.77412388938292166706201835989302381162652121371166681042319338645122967914165
    Line 773, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.32844709371329293481204341993662498915958835825472007097055531140469485536510
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.111421915063910125390468223727104279816132020122127048220680750209795138742359
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 3.192s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.47082215465676047411339173325449376899041321237205465639835857914341639510368
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 14.140s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.30929561680090777699048678119269226004762506601718395608399272552784911302192
    Line 899, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.10015593032864850449900818516603601405800039471586654020971851285429754491280
    Line 623, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14807957166160924947155925729418656672525241019607467028420604474707814982901
    Line 926, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.100818253682558534757803758985687428371631077493535739167178450583863734206846
    Line 868, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.31584251966587057474819003854542118651683853262490268244400416716151085794497
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3460.962700 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3460.962700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110661) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.89686232772162973838146775920111421527285763579896178928455675531838060199195
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3621.356800 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110661) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3621.356800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.111535299160531825759311536059894167031894799483076873623845675840945877026099
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3471.984404 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3471.984404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.52099790686650503047077567042408364925967539644504582614133051699153356887123
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2706.359776 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2706.359776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.99078519228275875392540156707061531007842783146098672439752202880285365000022
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2749.776683 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2749.776683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.73487156469224292355884165164450538671062936567699473079727962749097767989036
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2400.381600 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2400.381600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.83842118460069069471508106333750695645817297719518680697563224420248726403424
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3742.800000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3742.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.103552516722115620425300573186845608328509024169017176236344758064280814785996
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2793.125000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2793.125000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.107697727446072524583489800888616143801418544481567936177061452684789465867767
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 21591.589779 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 21591.589779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.15728045379362113074472659607925976651158333914735917440058921634899755392614
    Line 459, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3877.069296 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3877.069296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.17254870999122285120018688675885621991483435260471617140604561586733825174732
    Line 825, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.84088429132450702059957142775322712327882388986361830760293897838897448340376
    Line 785, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otbn_smoketest has 1 failures.
  - 0.chip_sw_otbn_smoketest.79629842916237386472736599469514906153535847975222613477894268993004522415121
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest/run.log
```
  UVM_ERROR @ 12019.620716 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.620716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32367) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.49267133314365012218979307795925628732097464565118529955077139794713903335261
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2440.918188 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32367) { a_addr: 'h105d0  a_data: 'h5c7ec4f1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h1ae51  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2440.918188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---