ADC_CTRL Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.780s	5.795ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.980s	1.288ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.220s	371.378us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	7.530s	32.028ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.470s	870.802us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.950s	613.151us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.220s	371.378us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	870.802us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	5.104m	332.977ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	57.040s	165.085ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.805m	500.597ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.508m	330.802ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	7.645m	646.652ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.312m	201.425ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.881m	177.517ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	10.021m	433.334ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.360s	4.610ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	19.000s	34.076ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	58.250s	120.152ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.039m	251.832ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.810s	310.010us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.040s	468.425us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.220s	628.978us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.220s	628.978us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.980s	1.288ms	1	1	100.00
		adc_ctrl_csr_rw	2.220s	371.378us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	870.802us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.850s	4.760ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.980s	1.288ms	1	1	100.00
		adc_ctrl_csr_rw	2.220s	371.378us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	870.802us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.850s	4.760ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	7.920s	4.237ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.320s	4.316ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.320s	4.316ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.340s	178.646ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.110694406954375718053830794658233645986418667776711746114149261772921985553057
      Line 239, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 178646140866 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 178646140866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---