AES/UNMASKED Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	60.644us	1	1	100.00
V1	smoke	aes_smoke	4.000s	59.175us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	239.660us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	53.987us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.034ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	186.661us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	100.749us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	53.987us	1	1	100.00
		aes_csr_aliasing	5.000s	186.661us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	4.000s	59.175us	1	1	100.00
		aes_config_error	4.000s	139.244us	1	1	100.00
		aes_stress	4.000s	66.063us	1	1	100.00
V2	key_length	aes_smoke	4.000s	59.175us	1	1	100.00
		aes_config_error	4.000s	139.244us	1	1	100.00
		aes_stress	4.000s	66.063us	1	1	100.00
V2	back2back	aes_stress	4.000s	66.063us	1	1	100.00
		aes_b2b	6.000s	162.692us	1	1	100.00
V2	backpressure	aes_stress	4.000s	66.063us	1	1	100.00
V2	multi_message	aes_smoke	4.000s	59.175us	1	1	100.00
		aes_config_error	4.000s	139.244us	1	1	100.00
		aes_stress	4.000s	66.063us	1	1	100.00
		aes_alert_reset	5.000s	140.174us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	278.376us	1	1	100.00
		aes_config_error	4.000s	139.244us	1	1	100.00
		aes_alert_reset	5.000s	140.174us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	94.563us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	653.970us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	140.174us	1	1	100.00
V2	stress	aes_stress	4.000s	66.063us	1	1	100.00
V2	sideload	aes_stress	4.000s	66.063us	1	1	100.00
		aes_sideload	5.000s	115.952us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	1.074ms	1	1	100.00
V2	stress_all	aes_stress_all	6.000s	144.095us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	69.158us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	106.233us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	106.233us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	239.660us	1	1	100.00
		aes_csr_rw	4.000s	53.987us	1	1	100.00
		aes_csr_aliasing	5.000s	186.661us	1	1	100.00
		aes_same_csr_outstanding	5.000s	81.217us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	239.660us	1	1	100.00
		aes_csr_rw	4.000s	53.987us	1	1	100.00
		aes_csr_aliasing	5.000s	186.661us	1	1	100.00
		aes_same_csr_outstanding	5.000s	81.217us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	141.280us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	477.222us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	590.561us	1	1	100.00
		aes_tl_intg_err	5.000s	364.126us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	364.126us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	140.174us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	59.175us	1	1	100.00
		aes_stress	4.000s	66.063us	1	1	100.00
		aes_alert_reset	5.000s	140.174us	1	1	100.00
		aes_core_fi	5.000s	240.811us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	66.014us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	54.854us	1	1	100.00
		aes_stress	4.000s	66.063us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	66.063us	1	1	100.00
		aes_sideload	5.000s	115.952us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	54.854us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	54.854us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	54.854us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	54.854us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	54.854us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	66.063us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	66.063us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	69.522us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	69.522us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	104.932us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	69.522us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	140.174us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_ctr_fi	4.000s	48.656us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	69.522us	1	1	100.00
		aes_control_fi	5.000s	46.640us	1	1	100.00
		aes_cipher_fi	5.000s	104.932us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.000s	33.712us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.26511653144010643609439991137891766732510513251486352440846037906666179719169
      Line 222, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  33711594 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  33711594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---