EDN Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.730s	18.875us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.520s	44.693us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.550s	31.680us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.670s	257.918us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.210s	177.227us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.910s	19.495us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.550s	31.680us	1	1	100.00
		edn_csr_aliasing	2.210s	177.227us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.660s	120.730us	1	1	100.00
V2	csrng_commands	edn_genbits	2.660s	120.730us	1	1	100.00
V2	genbits	edn_genbits	2.660s	120.730us	1	1	100.00
V2	interrupts	edn_intr	1.670s	30.034us	1	1	100.00
V2	alerts	edn_alert	2.050s	133.363us	1	1	100.00
V2	errs	edn_err	2.030s	92.335us	1	1	100.00
V2	disable	edn_disable	1.840s	58.200us	1	1	100.00
		edn_disable_auto_req_mode	2.040s	158.092us	1	1	100.00
V2	stress_all	edn_stress_all	4.260s	253.597us	1	1	100.00
V2	intr_test	edn_intr_test	1.620s	16.861us	1	1	100.00
V2	alert_test	edn_alert_test	1.810s	157.551us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.520s	149.932us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.520s	149.932us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.520s	44.693us	1	1	100.00
		edn_csr_rw	1.550s	31.680us	1	1	100.00
		edn_csr_aliasing	2.210s	177.227us	1	1	100.00
		edn_same_csr_outstanding	2.090s	35.098us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.520s	44.693us	1	1	100.00
		edn_csr_rw	1.550s	31.680us	1	1	100.00
		edn_csr_aliasing	2.210s	177.227us	1	1	100.00
		edn_same_csr_outstanding	2.090s	35.098us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.360s	271.167us	1	1	100.00
		edn_tl_intg_err	2.630s	490.523us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.780s	51.284us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.050s	133.363us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.360s	271.167us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.360s	271.167us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.360s	271.167us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.360s	271.167us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.050s	133.363us	1	1	100.00
		edn_sec_cm	4.360s	271.167us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.050s	133.363us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.630s	490.523us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	17.190s	2.039ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00