ENTROPY_SRC Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 29.760us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 34.792us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 37.858us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 9.000s 807.628us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 260.350us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 175.995us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 37.858us 1 1 100.00
entropy_src_csr_aliasing 9.000s 260.350us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 29.760us 1 1 100.00
entropy_src_rng 4.000s 23.485us 0 1 0.00
entropy_src_fw_ov 17.000s 3.200ms 0 1 0.00
V2 firmware_mode entropy_src_fw_ov 17.000s 3.200ms 0 1 0.00
V2 rng_mode entropy_src_rng 4.000s 23.485us 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 5.000s 27.514us 0 1 0.00
V2 health_checks entropy_src_rng 4.000s 23.485us 0 1 0.00
V2 conditioning entropy_src_rng 4.000s 23.485us 0 1 0.00
V2 interrupts entropy_src_rng 4.000s 23.485us 0 1 0.00
entropy_src_intr 7.000s 124.629us 1 1 100.00
V2 alerts entropy_src_rng 4.000s 23.485us 0 1 0.00
entropy_src_functional_alerts 6.000s 201.085us 1 1 100.00
V2 stress_all entropy_src_stress_all 2.067m 7.148ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 10.000s 1.470ms 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 69.974us 1 1 100.00
V2 alert_test entropy_src_alert_test 4.000s 29.967us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.000s 32.158us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.000s 32.158us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 34.792us 1 1 100.00
entropy_src_csr_rw 5.000s 37.858us 1 1 100.00
entropy_src_csr_aliasing 9.000s 260.350us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 23.737us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 34.792us 1 1 100.00
entropy_src_csr_rw 5.000s 37.858us 1 1 100.00
entropy_src_csr_aliasing 9.000s 260.350us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 23.737us 1 1 100.00
V2 TOTAL 8 12 66.67
V2S tl_intg_err entropy_src_sec_cm 4.000s 61.232us 1 1 100.00
entropy_src_tl_intg_err 7.000s 213.370us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.000s 23.485us 0 1 0.00
entropy_src_cfg_regwen 4.000s 15.287us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.000s 23.485us 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 4.000s 23.485us 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.000s 23.485us 0 1 0.00
entropy_src_fw_ov 17.000s 3.200ms 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
entropy_src_sec_cm 4.000s 61.232us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
entropy_src_sec_cm 4.000s 61.232us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.000s 23.485us 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
entropy_src_sec_cm 4.000s 61.232us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
entropy_src_sec_cm 4.000s 61.232us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 32.000s 10.140ms 0 1 0.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 201.085us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 213.370us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 12.000s 379.910us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 17 22 77.27

Failure Buckets