HMAC Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.890s 1.806ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.660s 39.565us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.500s 30.355us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.210s 1.679ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.030s 451.925us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.950s 41.165us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.500s 30.355us 1 1 100.00
hmac_csr_aliasing 3.030s 451.925us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.520s 15.589ms 1 1 100.00
V2 back_pressure hmac_back_pressure 6.370s 516.204us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.470s 317.984us 1 1 100.00
hmac_test_sha384_vectors 6.879m 12.638ms 1 1 100.00
hmac_test_sha512_vectors 6.225m 12.544ms 1 1 100.00
hmac_test_hmac256_vectors 8.490s 1.105ms 1 1 100.00
hmac_test_hmac384_vectors 10.330s 1.398ms 1 1 100.00
hmac_test_hmac512_vectors 11.270s 3.594ms 1 1 100.00
V2 burst_wr hmac_burst_wr 14.570s 1.491ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 20.788m 37.982ms 1 1 100.00
V2 error hmac_error 4.770s 1.271ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 10.000s 5.513ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.890s 1.806ms 1 1 100.00
hmac_long_msg 48.520s 15.589ms 1 1 100.00
hmac_back_pressure 6.370s 516.204us 1 1 100.00
hmac_datapath_stress 20.788m 37.982ms 1 1 100.00
hmac_burst_wr 14.570s 1.491ms 1 1 100.00
hmac_stress_all 2.420m 96.287ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.890s 1.806ms 1 1 100.00
hmac_long_msg 48.520s 15.589ms 1 1 100.00
hmac_back_pressure 6.370s 516.204us 1 1 100.00
hmac_datapath_stress 20.788m 37.982ms 1 1 100.00
hmac_wipe_secret 10.000s 5.513ms 1 1 100.00
hmac_test_sha256_vectors 8.470s 317.984us 1 1 100.00
hmac_test_sha384_vectors 6.879m 12.638ms 1 1 100.00
hmac_test_sha512_vectors 6.225m 12.544ms 1 1 100.00
hmac_test_hmac256_vectors 8.490s 1.105ms 1 1 100.00
hmac_test_hmac384_vectors 10.330s 1.398ms 1 1 100.00
hmac_test_hmac512_vectors 11.270s 3.594ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.890s 1.806ms 1 1 100.00
hmac_long_msg 48.520s 15.589ms 1 1 100.00
hmac_back_pressure 6.370s 516.204us 1 1 100.00
hmac_datapath_stress 20.788m 37.982ms 1 1 100.00
hmac_burst_wr 14.570s 1.491ms 1 1 100.00
hmac_error 4.770s 1.271ms 1 1 100.00
hmac_wipe_secret 10.000s 5.513ms 1 1 100.00
hmac_test_sha256_vectors 8.470s 317.984us 1 1 100.00
hmac_test_sha384_vectors 6.879m 12.638ms 1 1 100.00
hmac_test_sha512_vectors 6.225m 12.544ms 1 1 100.00
hmac_test_hmac256_vectors 8.490s 1.105ms 1 1 100.00
hmac_test_hmac384_vectors 10.330s 1.398ms 1 1 100.00
hmac_test_hmac512_vectors 11.270s 3.594ms 1 1 100.00
hmac_stress_all 2.420m 96.287ms 1 1 100.00
V2 stress_all hmac_stress_all 2.420m 96.287ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 19.572us 1 1 100.00
V2 intr_test hmac_intr_test 1.460s 30.268us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.940s 104.631us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.940s 104.631us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.660s 39.565us 1 1 100.00
hmac_csr_rw 1.500s 30.355us 1 1 100.00
hmac_csr_aliasing 3.030s 451.925us 1 1 100.00
hmac_same_csr_outstanding 2.510s 66.162us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.660s 39.565us 1 1 100.00
hmac_csr_rw 1.500s 30.355us 1 1 100.00
hmac_csr_aliasing 3.030s 451.925us 1 1 100.00
hmac_same_csr_outstanding 2.510s 66.162us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.610s 378.820us 1 1 100.00
hmac_tl_intg_err 2.230s 201.557us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.230s 201.557us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.890s 1.806ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.160s 1.072ms 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 22.960s 1.543ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.720s 32.462us 1 1 100.00
TOTAL 28 28 100.00