I2C Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: `ebd55f1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.000s	2.006ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.760s	5.085ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	41.080us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.650s	27.491us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.850s	372.433us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.940s	199.974us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.830s	89.596us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.650s	27.491us	1	1	100.00
		i2c_csr_aliasing	1.940s	199.974us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.140s	143.900us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.328m	26.093ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	42.620s	18.634ms	1	1	100.00
V2	host_override	i2c_host_override	1.570s	29.649us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	56.180s	4.364ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	20.450s	1.415ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.910s	525.293us	1	1	100.00
		i2c_host_fifo_fmt_empty	15.610s	2.620ms	1	1	100.00
		i2c_host_fifo_reset_rx	6.670s	162.494us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.253m	2.145ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.090s	852.704us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.410s	273.322us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.650s	8.673ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	29.820s	18.167ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.070s	1.313ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	37.810s	4.840ms	1	1	100.00
		i2c_target_intr_smoke	5.740s	6.301ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.020s	211.818us	1	1	100.00
		i2c_target_fifo_reset_tx	1.680s	300.449us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	27.670s	34.936ms	1	1	100.00
		i2c_target_stress_rd	37.810s	4.840ms	1	1	100.00
		i2c_target_intr_stress_wr	11.190s	8.390ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.720s	4.252ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.240s	1.535ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.940s	1.765ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.660s	680.182us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.720s	2.277ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.160s	792.491us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	42.620s	18.634ms	1	1	100.00
		i2c_host_perf_precise	2.280s	206.226us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.090s	852.704us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.240s	312.869us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.950s	888.209us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	499.774us	1	1	100.00
		i2c_target_nack_txstretch	2.650s	314.080us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.960s	4.030ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.660s	1.017ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.520s	34.702us	1	1	100.00
V2	intr_test	i2c_intr_test	1.640s	20.647us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.800s	92.295us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.800s	92.295us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	41.080us	1	1	100.00
		i2c_csr_rw	1.650s	27.491us	1	1	100.00
		i2c_csr_aliasing	1.940s	199.974us	1	1	100.00
		i2c_same_csr_outstanding	2.110s	56.955us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	41.080us	1	1	100.00
		i2c_csr_rw	1.650s	27.491us	1	1	100.00
		i2c_csr_aliasing	1.940s	199.974us	1	1	100.00
		i2c_same_csr_outstanding	2.110s	56.955us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.010s	97.727us	1	1	100.00
		i2c_sec_cm	1.650s	550.178us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.010s	97.727us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.010s	710.951us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.820s	100.087us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.930s	908.864us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.48792772651654580591768715791510762575537778591743390319382240568929584646134
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 710951297 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 710951297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.43543625892705203645142718854304665754988079102687002029369354085270580655260
    Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 908863592 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 908863592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.45524054230388124380593297363106504273598466955722601885620314490012306199119
Line 295, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26093239787 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1179438

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.53324615719493649959333604428933746644088091451554943481684230404769523573993
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 100086663 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 100086663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.40487663054917511559326161417174141030264391465834751232691908538960188262389
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 314079743 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 314079743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```