KMAC/MASKED Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.720s	749.966us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.920s	77.339us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	49.767us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.630s	148.538us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.520s	141.802us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	25.538us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	49.767us	1	1	100.00
		kmac_csr_aliasing	6.520s	141.802us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.890s	22.776us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.020s	121.451us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.025m	42.486ms	1	1	100.00
V2	burst_write	kmac_burst_write	17.078m	74.506ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.870m	63.861ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.470s	2.419ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.728m	67.843ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.351m	9.932ms	1	1	100.00
		kmac_test_vectors_shake_128	2.860m	41.717ms	1	1	100.00
		kmac_test_vectors_shake_256	1.413m	22.599ms	1	1	100.00
		kmac_test_vectors_kmac	4.150s	276.346us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.000s	100.004us	1	1	100.00
V2	sideload	kmac_sideload	3.916m	18.383ms	1	1	100.00
V2	app	kmac_app	41.950s	1.711ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.130m	9.117ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.733m	59.303ms	1	1	100.00
V2	error	kmac_error	3.710m	28.684ms	1	1	100.00
V2	key_error	kmac_key_error	8.500s	4.597ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.510s	481.691us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.920s	110.842us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.070s	87.618us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.460s	6.726ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.420s	50.553us	1	1	100.00
V2	stress_all	kmac_stress_all	4.105m	56.455ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.560s	40.725us	1	1	100.00
V2	alert_test	kmac_alert_test	1.880s	58.161us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.230s	441.601us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.230s	441.601us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.920s	77.339us	1	1	100.00
		kmac_csr_rw	1.810s	49.767us	1	1	100.00
		kmac_csr_aliasing	6.520s	141.802us	1	1	100.00
		kmac_same_csr_outstanding	2.890s	171.226us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.920s	77.339us	1	1	100.00
		kmac_csr_rw	1.810s	49.767us	1	1	100.00
		kmac_csr_aliasing	6.520s	141.802us	1	1	100.00
		kmac_same_csr_outstanding	2.890s	171.226us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.190s	80.198us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.190s	80.198us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.190s	80.198us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.190s	80.198us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.500s	92.764us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	57.120s	4.682ms	1	1	100.00
		kmac_tl_intg_err	2.960s	343.746us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.960s	343.746us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.420s	50.553us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.720s	749.966us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.916m	18.383ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.190s	80.198us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	57.120s	4.682ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	57.120s	4.682ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	57.120s	4.682ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.720s	749.966us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.420s	50.553us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	57.120s	4.682ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.025m	11.428ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.720s	749.966us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.843m	17.420ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.20604748331306052597758480223775669279841559819890124517206089563251848287400
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @  92764123 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @  92764123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---