KMAC/UNMASKED Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.390s	1.570ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.310s	58.843us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.730s	52.770us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.090s	3.457ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.610s	2.152ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	116.029us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.730s	52.770us	1	1	100.00
		kmac_csr_aliasing	7.610s	2.152ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.710s	14.680us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.290s	121.776us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.690s	4.093ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.574m	13.923ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.790s	1.219ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.070s	6.805ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.650s	7.006ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.100m	17.960ms	1	1	100.00
		kmac_test_vectors_shake_128	28.523m	205.565ms	1	1	100.00
		kmac_test_vectors_shake_256	1.437m	35.552ms	1	1	100.00
		kmac_test_vectors_kmac	2.870s	157.576us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.640s	111.138us	1	1	100.00
V2	sideload	kmac_sideload	1.666m	21.680ms	1	1	100.00
V2	app	kmac_app	1.739m	19.447ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.621m	5.708ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	19.770s	5.277ms	1	1	100.00
V2	error	kmac_error	1.480m	6.268ms	1	1	100.00
V2	key_error	kmac_key_error	8.310s	4.237ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.650s	189.454us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.210s	4.537ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.990s	244.586us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.860s	3.810ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.370s	92.616us	1	1	100.00
V2	stress_all	kmac_stress_all	28.050s	1.621ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.740s	19.526us	1	1	100.00
V2	alert_test	kmac_alert_test	1.950s	45.531us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.410s	50.166us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.410s	50.166us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.310s	58.843us	1	1	100.00
		kmac_csr_rw	1.730s	52.770us	1	1	100.00
		kmac_csr_aliasing	7.610s	2.152ms	1	1	100.00
		kmac_same_csr_outstanding	2.190s	65.355us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.310s	58.843us	1	1	100.00
		kmac_csr_rw	1.730s	52.770us	1	1	100.00
		kmac_csr_aliasing	7.610s	2.152ms	1	1	100.00
		kmac_same_csr_outstanding	2.190s	65.355us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.430s	1.118ms	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.430s	1.118ms	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.430s	1.118ms	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.430s	1.118ms	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.540s	542.867us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.260s	16.787ms	1	1	100.00
		kmac_tl_intg_err	1.770s	16.312us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.770s	16.312us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.370s	92.616us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.390s	1.570ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.666m	21.680ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.430s	1.118ms	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.260s	16.787ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.260s	16.787ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.260s	16.787ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.390s	1.570ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.370s	92.616us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.260s	16.787ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.587m	81.245ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.390s	1.570ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.280s	2.092ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.3639630690855400656973934369990468900061195220088391115103519755691991299245
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  16311944 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  16311944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---