PATTGEN Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	33.142us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	11.738us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	48.897us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	126.379us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	21.510us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	26.172us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	48.897us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.510us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	4.000s	28.052us	1	1	100.00
V2	cnt_rollover	cnt_rollover	1.150m	10.523ms	1	1	100.00
V2	error	pattgen_error	5.000s	80.228us	1	1	100.00
V2	stress_all	pattgen_stress_all	18.000s	1.450ms	1	1	100.00
V2	alert_test	pattgen_alert_test	4.000s	29.484us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	35.256us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	45.651us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	45.651us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	11.738us	1	1	100.00
		pattgen_csr_rw	4.000s	48.897us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.510us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	58.551us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	11.738us	1	1	100.00
		pattgen_csr_rw	4.000s	48.897us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.510us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	58.551us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	55.680us	1	1	100.00
		pattgen_sec_cm	4.000s	63.385us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	55.680us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	11.000s	3.722ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	5.000s	33.916us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.76945817993303934191907517017541659394200801826788168018614415873268232763427
      Line 249, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3688049424 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 3688071893 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3688071893 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 5/5
        UVM_INFO @ 3688431893 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]