ROM_CTRL/32KB Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.080s 592.095us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.750s 298.991us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.940s 558.676us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.900s 554.110us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.250s 384.603us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.020s 315.614us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.940s 558.676us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 384.603us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.350s 553.022us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.230s 294.009us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.650s 938.325us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.090s 780.194us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 9.180s 303.520us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.560s 533.753us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.640s 416.796us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.640s 416.796us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.750s 298.991us 1 1 100.00
rom_ctrl_csr_rw 4.940s 558.676us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 384.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.020s 558.679us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.750s 298.991us 1 1 100.00
rom_ctrl_csr_rw 4.940s 558.676us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 384.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.020s 558.679us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.930s 2.114ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
rom_ctrl_tl_intg_err 25.250s 352.770us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.080s 592.095us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.080s 592.095us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.080s 592.095us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 25.250s 352.770us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
rom_ctrl_kmac_err_chk 9.180s 303.520us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 39.480s 959.158us 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.930s 2.114ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.000m 2.212ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.977m 9.408ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00