ROM_CTRL/64KB Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.970s 771.962us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.770s 604.010us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.030s 1.069ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.730s 992.343us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.420s 601.416us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.850s 5.099ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.030s 1.069ms 1 1 100.00
rom_ctrl_csr_aliasing 7.420s 601.416us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.740s 1.068ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.330s 1.071ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.730s 666.999us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 23.600s 1.442ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.080s 1.061ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.520s 554.401us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.500s 1.070ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.500s 1.070ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.770s 604.010us 1 1 100.00
rom_ctrl_csr_rw 7.030s 1.069ms 1 1 100.00
rom_ctrl_csr_aliasing 7.420s 601.416us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 557.331us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.770s 604.010us 1 1 100.00
rom_ctrl_csr_rw 7.030s 1.069ms 1 1 100.00
rom_ctrl_csr_aliasing 7.420s 601.416us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 557.331us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 56.100s 24.858ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
rom_ctrl_tl_intg_err 41.210s 400.752us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.970s 771.962us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.970s 771.962us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.970s 771.962us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 41.210s 400.752us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 14.080s 1.061ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 56.100s 24.858ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.155m 1.073ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.132m 3.353ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets