ebd55f1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.720s | 1.940ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 4.270s | 1.173ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.020s | 156.137us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 12.540s | 16.192ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.250s | 1.081ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 13.290s | 7.111ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.900s | 3.028ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 11.330s | 16.826ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.470m | 159.416ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 4.110s | 1.310ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 2.740s | 708.298us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.690s | 560.115us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.680s | 143.951us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.570s | 128.354us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.620s | 1.227ms | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 2.160s | 338.157us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.610s | 446.828us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 4.110s | 1.310ms | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.960s | 233.056us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.910s | 744.036us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.690s | 560.115us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.700s | 162.995us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 3.140s | 190.070us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.580s | 141.916us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 26.280s | 9.898ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 17.960s | 933.239us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 1.650s | 51.851us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 17.960s | 933.239us | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 2.580s | 141.916us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 1.600s | 56.538us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 1.590s | 92.259us | 1 | 1 | 100.00 |
| V1 | TOTAL | 26 | 27 | 96.30 | |||
| V2 | idcode | rv_dm_smoke | 3.720s | 1.940ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.880s | 133.646us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.570s | 544.565us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.810s | 165.325us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.300s | 269.487us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 4.010s | 1.051ms | 1 | 1 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 1.790s | 66.664us | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 1.870s | 92.794us | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.040s | 391.909us | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.110s | 492.754us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 2.510s | 1.109ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 2.720s | 687.040us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.580s | 74.660us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 6.470s | 12.473ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 2.290s | 93.751us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 1.680s | 103.424us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 11.360s | 5.045ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_dm_alert_test | 1.730s | 42.160us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 1.820s | 48.205us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 1.820s | 48.205us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 17.960s | 933.239us | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 3.140s | 190.070us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.580s | 141.916us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 4.190s | 1.068ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 17.960s | 933.239us | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 3.140s | 190.070us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.580s | 141.916us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 4.190s | 1.068ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 13 | 19 | 68.42 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.730s | 693.167us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 12.770s | 7.540ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 12.770s | 7.540ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.510s | 1.109ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.630s | 30.203us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.510s | 1.109ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.630s | 30.203us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.720s | 1.940ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 2.020s | 198.221us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.880s | 87.202us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.880s | 87.202us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 2.020s | 198.221us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 2.120s | 122.610us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 1.740s | 11.614us | 1 | 1 | 100.00 | |
| TOTAL | 45 | 53 | 84.91 |
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.5620433788073320023887055475828166637972258929617184098380585572918842062089
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.115161836799935933621533107673189165342416031668250195815049927925815242197377
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.23914287709933416588922693694291090462089990017113882286566459640243318680368
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.30737135645474893986830378793159468139725451814517074866402998850201159866421
Line 94, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 290
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@16311) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.25408756811072450067640503345305380855037319023248915642733907858294342718204
Line 80, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 93751182 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@16311) { a_addr: 'h360fa108 a_data: 'h83c339f6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc0 a_opcode: 'h4 a_user: 'h1b066 d_param: 'h0 d_source: 'hc0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 93751182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@15571) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.58687589235143351000245355397651941024048006826176086472637114164227322652897
Line 80, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 122609940 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@15571) { a_addr: 'h770675a4 a_data: 'h3fb5e2b0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h1a6d1 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 122609940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5789) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.74827772794328504572817179304524921662341653187933242231165442606872835372290
Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 48204810 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5789) { a_addr: 'he64fb608 a_data: 'hd1db9585 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4c a_opcode: 'h4 a_user: 'h1bbd3 d_param: 'h0 d_source: 'h4c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 48204810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5561) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.6547901033803263520361247048608791852868618248371689691388012716882229640218
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 51850634 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5561) { a_addr: 'hf4330660 a_data: 'h780df238 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8d a_opcode: 'h4 a_user: 'h1b3ae d_param: 'h0 d_source: 'h8d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 51850634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---