RV_TIMER Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	14.787m	150.714ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.630s	51.892us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.460s	15.904us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.760s	316.904us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.720s	55.614us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.730s	372.664us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.460s	15.904us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	55.614us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.550s	70.028us	1	1	100.00
V2	disabled	rv_timer_disabled	1.985m	440.358ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	20.320s	28.373ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	20.320s	28.373ms	1	1	100.00
V2	stress	rv_timer_stress_all	6.387m	353.731ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.500s	48.494us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.230s	657.267us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.230s	657.267us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.630s	51.892us	1	1	100.00
		rv_timer_csr_rw	1.460s	15.904us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	55.614us	1	1	100.00
		rv_timer_same_csr_outstanding	1.770s	119.150us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.630s	51.892us	1	1	100.00
		rv_timer_csr_rw	1.460s	15.904us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	55.614us	1	1	100.00
		rv_timer_same_csr_outstanding	1.770s	119.150us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.000s	123.209us	1	1	100.00
		rv_timer_tl_intg_err	2.100s	449.175us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.100s	449.175us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	2.250s	443.680us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.86510192443048925565191226547578307273116440364673628780868246757999791822802
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 443679834 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 443679834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---