SPI_DEVICE/1R1W Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	25.000s	9.305ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.170s	20.904us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	47.157us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.770s	705.892us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.720s	839.221us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.120s	88.481us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	47.157us	1	1	100.00
		spi_device_csr_aliasing	15.720s	839.221us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.540s	28.454us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.140s	146.337us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.590s	20.915us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	6.947us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	4.658us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.160s	259.429us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.160s	259.429us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.300s	1.496ms	1	1	100.00
		spi_device_tpm_sts_read	1.760s	87.376us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.230s	353.615us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.590s	10.844ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.720s	1.656ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.720s	1.656ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	21.330s	4.689ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	21.330s	4.689ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.330s	4.689ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	21.330s	4.689ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.330s	4.689ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.000s	4.303ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.300s	1.251ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.300s	1.251ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.300s	1.251ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.840s	43.731us	1	1	100.00
		spi_device_read_buffer_direct	11.250s	1.189ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.300s	1.251ms	1	1	100.00
		spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.542m	31.271ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.950s	393.987us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.950s	393.987us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	25.000s	9.305ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.957m	37.664ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.954m	58.265ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.650s	15.939us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	28.291us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.340s	1.105ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.340s	1.105ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.170s	20.904us	1	1	100.00
		spi_device_csr_rw	2.750s	47.157us	1	1	100.00
		spi_device_csr_aliasing	15.720s	839.221us	1	1	100.00
		spi_device_same_csr_outstanding	3.650s	700.199us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.170s	20.904us	1	1	100.00
		spi_device_csr_rw	2.750s	47.157us	1	1	100.00
		spi_device_csr_aliasing	15.720s	839.221us	1	1	100.00
		spi_device_same_csr_outstanding	3.650s	700.199us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.750s	162.225us	1	1	100.00
		spi_device_tl_intg_err	9.020s	765.774us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.020s	765.774us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.765m	26.580ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.56142295339650333148329646572576405278856041646019681131034151268038943680695
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4697146 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[41])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4697146 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4697146 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[937])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.3067555536466243666411633266931174688580607859173577626113110735331401662915
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4132526 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4132526 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4166526 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe7b7b [11100111101101111011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4166526 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xe7b7b [11100111101101111011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])