SPI_DEVICE/2P Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.004m	4.968ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.630s	62.485us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.970s	34.054us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.090s	5.494ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.150s	154.679us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.210s	98.220us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.970s	34.054us	1	1	100.00
		spi_device_csr_aliasing	6.150s	154.679us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	12.353us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.180s	36.203us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.750s	20.442us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.010s	122.693us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.960s	1.865us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.920s	99.371us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.920s	99.371us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.120s	4.119ms	1	1	100.00
		spi_device_tpm_sts_read	1.620s	30.056us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.120s	818.736us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.970s	155.195us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.480s	6.072ms	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.480s	6.072ms	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.560s	116.161us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.560s	116.161us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.560s	116.161us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.560s	116.161us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.560s	116.161us	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.240s	6.918ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	43.290s	72.711ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	43.290s	72.711ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	43.290s	72.711ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	26.140s	3.868ms	1	1	100.00
		spi_device_read_buffer_direct	5.910s	1.194ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	43.290s	72.711ms	1	1	100.00
		spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	24.440s	3.693ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.250s	1.132ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.250s	1.132ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.004m	4.968ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	22.350s	5.191ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.388m	109.824ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.810s	34.528us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.570s	14.145us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.950s	824.381us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.950s	824.381us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.630s	62.485us	1	1	100.00
		spi_device_csr_rw	1.970s	34.054us	1	1	100.00
		spi_device_csr_aliasing	6.150s	154.679us	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	896.863us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.630s	62.485us	1	1	100.00
		spi_device_csr_rw	1.970s	34.054us	1	1	100.00
		spi_device_csr_aliasing	6.150s	154.679us	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	896.863us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.700s	38.791us	1	1	100.00
		spi_device_tl_intg_err	11.640s	2.649ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.640s	2.649ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.739m	98.484ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.70198443578333078379121715713885240496435345181463679692045672775069403587251
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1180652 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1180652 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1257652 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x3361f2 [1100110110000111110010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1257652 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)