SPI_HOST Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	21.000s	2.094ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	48.730us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	96.486us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	620.794us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	49.446us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	44.349us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	96.486us	1	1	100.00
		spi_host_csr_aliasing	3.000s	49.446us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.897us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	64.623us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	56.384us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	84.532us	1	1	100.00
		spi_host_error_cmd	4.000s	46.070us	1	1	100.00
		spi_host_event	15.000s	2.258ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	182.136us	1	1	100.00
V2	speed	spi_host_speed	5.000s	182.136us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	182.136us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	15.000s	1.171ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	129.435us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	182.136us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	182.136us	1	1	100.00
V2	duplex	spi_host_smoke	21.000s	2.094ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	21.000s	2.094ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	40.065us	1	1	100.00
V2	spien	spi_host_spien	7.000s	372.800us	1	1	100.00
V2	stall	spi_host_status_stall	27.000s	3.552ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	10.000s	15.084ms	0	1	0.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	84.532us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	21.762us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	16.077us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	57.631us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	57.631us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	48.730us	1	1	100.00
		spi_host_csr_rw	4.000s	96.486us	1	1	100.00
		spi_host_csr_aliasing	3.000s	49.446us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	24.159us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	48.730us	1	1	100.00
		spi_host_csr_rw	4.000s	96.486us	1	1	100.00
		spi_host_csr_aliasing	3.000s	49.446us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	24.159us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	88.112us	1	1	100.00
		spi_host_sec_cm	5.000s	40.911us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	88.112us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.433m	26.040ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
  • Test spi_host_idlecsbactive has 1 failures.

    • 0.spi_host_idlecsbactive.52204573518707746954622896657018054329634098583480689034123960619005492334058
      Line 157, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log

        UVM_FATAL @ 15083768936 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8baa3214, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
        UVM_INFO @ 15083768936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---